datapath.vhd

MIPS处理器VHDL代码

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:20:52 09/17/2007 
-- Design Name: 
-- Module Name:    datapath - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
use IEEE.STD_LOGIC_ARITH.all;

entity datapath is --MIPS 处理器的数据通路
    generic(width, regbits: integer);
    port(clk,reset:         in  STD_LOGIC;
     	   memdata:  	       in  STD_LOGIC_VECTOR(width-1 downto 0);
	      alusrca, memtoreg, iord, pcen,regwrite, regdst:  in  STD_LOGIC;
	      pcsource,alusrcb:  in  STD_LOGIC_VECTOR(1 downto 0);
	      irwrite: 	       in  STD_LOGIC_VECTOR(3 downto 0);
	      alucont: 	       in  STD_LOGIC_VECTOR(2 downto 0);
	      zero:		          out STD_LOGIC;
	      instr:		       out STD_LOGIC_VECTOR(31 downto 0);
	      adr, writedata:    out STD_LOGIC_VECTOR(width-1 downto 0));
end;


architecture struct of datapath is

   component alu generic(width: integer);
	port(a,b:               in  STD_LOGIC_VECTOR(width-1 downto 0);
	     alucont:           in  STD_LOGIC_VECTOR(2 downto 0);
	     result:            out STD_LOGIC_VECTOR(width-1 downto 0));
    end component;
	 
   component regfile generic(width,regbits: integer);
	   port(clk:            in  STD_LOGIC;
	        write:          in  STD_LOGIC;
	        ra1, ra2, wa:   in  STD_LOGIC_VECTOR(regbits-1 downto 0);
	        wd:             in  STD_LOGIC_VECTOR(width-1 downto 0);
	        rd1, rd2:       out STD_LOGIC_VECTOR(width-1 downto 0));
    end component;
	 
--    component regfile generic(width, regbits: integer);
--      port(a: in  STD_LOGIC_VECTOR(width-1 downto 0);
--	        y: out STD_LOGIC);
--    end component;
	 
    component flop generic(width: integer);
	    port(clk:           in  STD_LOGIC;
	         d:             in  STD_LOGIC_VECTOR(width-1 downto 0);
	         q:             out STD_LOGIC_VECTOR(width-1 downto 0));
    end component;
	 
    component flopen generic(width: integer);
	 port(clk,en:           in  STD_LOGIC;
	      d:                in  STD_LOGIC_VECTOR(width-1 downto 0);
	      q:                out STD_LOGIC_VECTOR(width-1 downto 0));
    end component;
	 
    component flopenr generic(width: integer);
	 port(clk,reset,en:     in  STD_LOGIC;
	      d:                in  STD_LOGIC_VECTOR(width-1 downto 0);
	      q:   	            out STD_LOGIC_VECTOR(width-1 downto 0));
    end component;
	 
    component mux2 generic(width: integer);
	 port(d0,d1:            in  STD_LOGIC_VECTOR(width-1 downto 0);
	      s:	               in  STD_LOGIC;
	      y:                out STD_LOGIC_VECTOR(width-1 downto 0));
    end component;
	 
    component mux4 generic(width: integer);
	 port(d0,d1,d2,d3: in  STD_LOGIC_VECTOR(width-1 downto 0);
	      s:	          in  STD_LOGIC_VECTOR(1 downto 0);
	      y:           out STD_LOGIC_VECTOR(width-1 downto 0));
    end component;
	 
    constant CONST_ONE:  STD_LOGIC_VECTOR(width-1 downto 0) := conv_std_logic_vector(1,width);
    constant CONST_ZERO: STD_LOGIC_VECTOR(width-1 downto 0) := conv_std_logic_vector(1,width);
    signal ra1, ra2, wa: STD_LOGIC_VECTOR(regbits-1 downto 0);
	 signal  wd,src2, constx4,src1,aluresult, aluout,rd2,dp_writedata,rd1, a,md,pc, nextpc: STD_LOGIC_VECTOR(width-1 downto 0);	 
    signal dp_instr: STD_LOGIC_VECTOR(31 downto 0);

begin
    constx4 <= dp_instr(width-3 downto 0) & "00";

    ra1 <= dp_instr(regbits+20 downto 21);
    ra2 <= dp_instr(regbits+15 downto 16);
    regmux:  mux2 generic map(regbits) port map(dp_instr(regbits+15 downto 16), dp_instr(regbits+10 downto 11),regdst,wa);

    ir0:      flopen  generic map(8)     port map(clk, irwrite(0), memdata(7 downto 0), dp_instr(7 downto 0));
    ir1:      flopen  generic map(8)     port map(clk, irwrite(0), memdata(7 downto 0), dp_instr(15 downto 8));
    ir2:      flopen  generic map(8)     port map(clk, irwrite(0), memdata(7 downto 0), dp_instr(23 downto 16));
    ir3:      flopen  generic map(8)     port map(clk, irwrite(0), memdata(7 downto 0), dp_instr(31 downto 24));

    pcreg:    flopenr generic map(width) port map(clk, reset, pcen, nextpc,pc);
    mdr:      flop    generic map(width) port map(clk, memdata, md);
    areg:     flop    generic map(width) port map(clk, rd1, a);
    wrd:      flop    generic map(width) port map(clk, rd2,dp_writedata);
    res:      flop    generic map(width) port map(clk, aluresult, aluout);
	 adrmux:   mux2    generic map(width) port map(aluresult, aluout, iord, adr);
	 
    src1mux:  mux2    generic map(width) port map(pc, a, alusrca, src1);
    src2mux:  mux4    generic map(width) port map(dp_writedata, CONST_ONE,dp_instr(width-1 downto 0), constx4, alusrcb, src2);
    pcmux:    mux4    generic map(width) port map(aluresult, aluout, constx4, CONST_ZERO, pcsource, nextpc);
    wdmux:    mux2    generic map(width) port map(aluout, md, memtoreg, wd);
    rf:       regfile generic map(width, regbits) 
	                                      port map(clk, regwrite, ra1, ra2, wa, wd, rd1, rd2);
    alunit:   alu     generic map(width) port map(src1,src2,alucont, aluresult);
--    zd:    zerodetect generic map(width) port map(aluresult, zero);
   
    instr <= dp_instr; writedata <= dp_writedata;
end;
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--------------------------------   ALU  --------------------------------------------------------------
library IEEE; 
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all; 
use IEEE.STD_LOGIC_UNSIGNED.all;

entity alu is  --