interrupt.lst

里面包括RS232和IIC对24LC256的读写代码 CYGNAL IDE打开项目

C51 COMPILER V7.05   INTERRUPT                                                             04/12/2005 09:13:15 PAGE 1   


C51 COMPILER V7.05, COMPILATION OF MODULE INTERRUPT
OBJECT MODULE PLACED IN interrupt.OBJ
COMPILER INVOKED BY: E:\Cygnal\IDEfiles\C51\BIN\C51.exe interrupt.c DB OE

stmt level    source

   1          #define INT_ISR_C
   2          
   3          
   4          #include "c8051F330.h"
   5          #include "rs232.h"
   6          
   7          
   8          char rece,count_UART,count_UART1;
   9          char Rec_OK,Tran_OK;
  10          char Tran_Flag;
  11          char xdata sRecComBuf[8];
  12          char *pointer;
  13          void UART_Isr(void)  interrupt 4
  14          {
  15   1              ES0 = 0x0;
  16   1              if(TI0)
  17   1                      {
  18   2                              SCON0 &=0xFD;
  19   2                              Tran_Flag=0;
  20   2                              if (count_UART1==8)
  21   2                                      Tran_OK=0x45;
  22   2                                      
  23   2                      }
  24   1              else
  25   1                      {
  26   2                              SCON0 &=0xFE;
  27   2                              *pointer++ = SBUF0;
  28   2                              count_UART++;
  29   2                              if (count_UART==8)
  30   2                              {
  31   3                                      Rec_OK=0x23;
  32   3                              }
  33   2                              
  34   2                      }
  35   1              ES0 = 0x1;       
  36   1      } 
  37          
  38          
  39          
  40          
  41          
  42          //------------------------------------------------------------------------------------
  43          // Timer3 Interrupt Service Routine (ISR)
  44          //------------------------------------------------------------------------------------
  45          //
  46          // A Timer3 interrupt indicates an SMBus SCL low timeout.
  47          // The SMBus is disabled and re-enabled here
  48          //
  49          void Timer3_ISR (void) interrupt 14
  50          {
  51   1         SMB0CF &= ~0x80;          // Disable SMBus
  52   1         SMB0CF |= 0x80;           // Re-enable SMBus
  53   1         TMR3CN &= ~0x80;          // Clear Timer3 interrupt-pending flag
  54   1      }
  55          
C51 COMPILER V7.05   INTERRUPT                                                             04/12/2005 09:13:15 PAGE 2   

  56          
  57          
  58          
  59          
  60          
  61          //------------------------------------------------------------------------------------
  62          // SMBus Interrupt Service Routine (ISR)
  63          //------------------------------------------------------------------------------------
  64          //
  65          // SMBus ISR state machine
  66          // - Master only implementation - no slave or arbitration states defined
  67          // - All incoming data is written starting at the global pointer <pSMB_DATA_IN>
  68          // - All outgoing data is read from the global pointer <pSMB_DATA_OUT>
  69          //
  70          void SMBus_ISR (void) interrupt 7
  71          {
  72   1         bit FAIL = 0;                             // Used by the ISR to flag failed
  73   1                                                   // transfers
  74   1      
  75   1         static char i;                            // Used by the ISR to count the
  76   1                                                   // number of data bytes sent or
  77   1                                                   // received
  78   1      
  79   1         static bit SEND_START = 0;                // Send a start
  80   1      
  81   1         switch (SMB0CN & 0xF0)                    // Status vector
  82   1         {
  83   2            // Master Transmitter/Receiver: START condition transmitted.
  84   2            case SMB_MTSTA:
  85   2               SMB0DAT = TARGET;                   // Load address of the target slave
  86   2               SMB0DAT |= SMB_RW;                  // Load R/W bit
  87   2               STA = 0;                            // Manually clear START bit
  88   2               i = 0;                              // reset data byte counter
  89   2               break;
  90   2      
  91   2            // Master Transmitter: Data byte (or Slave Address) transmitted
  92   2            case SMB_MTDB:
  93   2               if (ACK)                            // Slave Address or Data Byte
  94   2               {                                   // Acknowledged?
  95   3                  if (SEND_START)
  96   3                  {
  97   4                     STA = 1;
  98   4                     SEND_START = 0;
  99   4                     break;
 100   4                  }
 101   3                  if(SMB_SENDWORDADDR)             // Are we sending the word address?
 102   3                  {
 103   4                     SMB_SENDWORDADDR = 0;         // Clear flag
 104   4                     SMB0DAT = WORD_ADDR;          // send word's high 8bits address
 105   4      
 106   4                    /* if (SMB_RANDOMREAD)
 107   4                     {
 108   4                        SEND_START = 1;            // send a START after the next ACK cycle
 109   4                        SMB_RW = READ;
 110   4                     }*/
 111   4      
 112   4                     break;
 113   4                  }
 114   3      
 115   3                      else if(SMB_SENDWORDADDR1)             // Are we sending the word address?
 116   3                  {
 117   4                     SMB_SENDWORDADDR1 = 0;         // Clear flag
C51 COMPILER V7.05   INTERRUPT                                                             04/12/2005 09:13:15 PAGE 3   

 118   4                     SMB0DAT = WORD_ADDR1;          // send word's low 8bits address
 119   4      
 120   4                     if (SMB_RANDOMREAD)
 121   4                     {
 122   5                        SEND_START = 1;            // send a START after the next ACK cycle
 123   5                        SMB_RW = READ;
 124   5                     }
 125   4      
 126   4                     break;
 127   4                  }
 128   3      
 129   3                  if (SMB_RW==WRITE)               // Is this transfer a WRITE?
 130   3                  {
 131   4      
 132   4                     if (i < SMB_DATA_LEN)         // Is there data to send?
 133   4                     {
 134   5                        SMB0DAT = *pSMB_DATA_OUT;  // send data byte
 135   5                        pSMB_DATA_OUT++;           // increment data out pointer
 136   5                        i++;                       // increment number of bytes sent
 137   5                     }
 138   4                     else
 139   4                     {
 140   5                       STO = 1;                    // set STO to terminte transfer
 141   5                       SMB_BUSY = 0;               // clear software busy flag
 142   5                     }
 143   4                  }
 144   3                  else {}                          // If this transfer is a READ,
 145   3                                                   // then take no action. Slave
 146   3                                                   // address was transmitted. A
 147   3                                                   // separate 'case' is defined
 148   3                                                   // for data byte recieved.
 149   3               }
 150   2               else                                // If slave NACK,
 151   2               {
 152   3                  if(SMB_ACKPOLL)
 153   3                  {
 154   4                     STA = 1;                      // Restart transfer
 155   4                  }
 156   3                  else