lcd.h

intel pxa270的bootlader

#define XLLP_BIT_26   (1 << 26)
#define XLLP_BIT_27   (1 << 27)
#define XLLP_BIT_28   (1 << 28)
#define XLLP_BIT_29   (1 << 29)
#define XLLP_BIT_30   (1 << 30)
#define XLLP_BIT_31   (1 << 31)
#endif


#define XLLP_GPIO_BIT_PWM_OUT0	(1 << 16)
#define XLLP_GPIO_BIT_PWM_OUT1	(1 << 17)
#define XLLP_GPIO_BIT_CIF_MCLK        (1 << 23)
#define XLLP_GPIO_BIT_CIF_FV            (1 << 24)
#define XLLP_GPIO_BIT_CIF_LV            (1 << 25)

typedef struct  
{
	unsigned int FDADR;		// Pointer to next frame descriptor (Physical address)
	unsigned int FSADR;		// Pointer to the data (Physical address)
	unsigned int FIDR;		// Frame descriptor ID
	unsigned int LDCMD;		// DMA command
	unsigned int PHYSADDR;  // PHYSADDR contains the physical address of this descriptor.
}LCD_FRAME_DESCRIPTOR;

//
// LCD Controller Control Register 5 (LCCR5)
//
#define LCD_SOFM1		0x00000001
#define LCD_SOFM2		0x00000002
#define LCD_SOFM3		0x00000004
#define LCD_SOFM4		0x00000008
#define LCD_SOFM5		0x00000010
#define LCD_SOFM6		0x00000020
#define LCD_EOFM1		0x00000100
#define LCD_EOFM2		0x00000200
#define LCD_EOFM3		0x00000400
#define LCD_EOFM4		0x00000800
#define LCD_EOFM5		0x00001000
#define LCD_EOFM6		0x00002000
#define LCD_BSM1		0x00010000
#define LCD_BSM2		0x00020000
#define LCD_BSM3		0x00040000
#define LCD_BSM4		0x00080000
#define LCD_BSM5		0x00100000
#define LCD_BSM6		0x00200000
#define LCD_IUM1		0x01000000
#define LCD_IUM2		0x02000000
#define LCD_IUM3		0x04000000
#define LCD_IUM4		0x08000000
#define LCD_IUM5		0x10000000
#define LCD_IUM6		0x20000000

// LCD Controller Control Register 0 (LCCR0)
//
#define LCD_ENB		0x00000001
#define LCD_CMS		0x00000002
#define LCD_SDS		0x00000004
#define LCD_LDM		0x00000008
#define LCD_SFM		0x00000010
#define LCD_IUM		0x00000020
#define LCD_EFM		0x00000040
#define LCD_PAS		0x00000080
#define LCD_BLE		0x00000100
#define LCD_DPD		0x00000200
#define LCD_DIS		0x00000400
#define LCD_QDM		0x00000800
#define LCD_PDD(n)	((n) << 12)
#define LCD_BM		0x00100000
#define LCD_OUM		0x00200000
#define LCD_LCDT	0x00400000
#define LCD_RDSTM	0x00800000
#define LCD_CMDIM	0x01000000
#define LCD_OUC		0x02000000
#define LCD_LDDALT	0x04000000

//
// LCD Controller Control Register 1 (LCCR1)
//
#define LCD_PPL(n)	(n - 1)
#define LCD_HSW(n)	((n) << 10)
#define LCD_ELW(n)	((n) << 16)
#define LCD_BLW(n)	((n) << 24)

//
// LCD Controller Control Register 2 (LCCR2)
//
#define LCD_LPP(n)	((n) - 1)
#define LCD_VSW(n)	((n) << 10)
#define LCD_EFW(n)	((n) << 16)
#define LCD_BFW(n)	((n) << 24)

//
// LCD Controller Control Register 3 (LCCR3)
//
#define LCD_PCD(n)		((n))
#define LCD_ACB(n)		((n) << 8)
#define LCD_API(n)		((n) << 16)
#define LCD_VSP			0x00100000
#define LCD_HSP			0x00200000
#define LCD_PCP			0x00400000
#define LCD_OEP			0x00800000
#define LCD_DPC			0x08000000
#define LCD_BPP(n)		((((n) & 0x7) << 24) | (((n) & 0x8) << 26))
#define LCD_PDFOR(n)	((n) << 30)

//
// LCD Controller Control Register 4 (LCCR4)
//
#define LCD_K1(n)		((n))
#define LCD_K2(n)		((n) << 3)
#define LCD_K3(n)		((n) << 6)
#define LCD_PAL_FOR(n)	((n) << 15)


//
// LCD Controller Control Register 5 (LCCR5)
//
#define LCD_SOFM1		0x00000001
#define LCD_SOFM2		0x00000002
#define LCD_SOFM3		0x00000004
#define LCD_SOFM4		0x00000008
#define LCD_SOFM5		0x00000010
#define LCD_SOFM6		0x00000020
#define LCD_EOFM1		0x00000100
#define LCD_EOFM2		0x00000200
#define LCD_EOFM3		0x00000400
#define LCD_EOFM4		0x00000800
#define LCD_EOFM5		0x00001000
#define LCD_EOFM6		0x00002000
#define LCD_BSM1		0x00010000
#define LCD_BSM2		0x00020000
#define LCD_BSM3		0x00040000
#define LCD_BSM4		0x00080000
#define LCD_BSM5		0x00100000
#define LCD_BSM6		0x00200000
#define LCD_IUM1		0x01000000
#define LCD_IUM2		0x02000000
#define LCD_IUM3		0x04000000
#define LCD_IUM4		0x08000000
#define LCD_IUM5		0x10000000
#define LCD_IUM6		0x20000000

//
// LCD Controller Overlay Control Register OVL1C1
//
#define LCD_PPL1(n)		((n))
#define LCD_LPO1(n)		((n) << 10)
#define LCD_BPP1(n)		((n) << 20)
#define LCD_O1EN		0x80000000

//
// LCD Controller Overlay Control Register OVL1C2
//
#define LCD_O1XPOS(n)	((n))
#define LCD_01YPOS(n)	((n) << 10)

//
// LCD Controller Overlay Control Register OVL2C1
//
#define LCD_PPL2(n)		((n))
#define LCD_LPO2(n)		((n) << 10)
#define LCD_BPP2(n)		((n) << 20)
#define LCD_O2EN		0x80000000

//
// LCD Controller Overlay Control Register OVL2C2
//
#define LCD_O2XPOS(n)	((n))
#define LCD_O2YPOS(n)	((n) << 10)
#define LCD_FOR(n)		((n) << 20)

//
// LCD Controller Cursor Control Register (CCR)
//
#define LCD_CURMS(n)	((n))
#define LCD_CXPOS(n)	((n) << 5)
#define LCD_CYPOS(n)	((n) << 15)
#define LCD_CEN			0x80000000

//
// LCD Controller Command Control Register (CMDCR)
//
#define LCD_SYNC_CNT(n)	((n))

//
// LCD Controller Panel Read Status Register (PRSR)
//
#define LCD_DATA(n)		((n) & 0xff)
#define LCD_A0			0x00000100
#define LCD_ST_OK		0x00000200
#define LCD_CON_ST		0x00000400


//
// LCD Controller Status Register (LCSR0)
//
#define LCD_LDD			0x00000001
#define LCD_SOF0		0x00000002
#define LCD_BER			0x00000004
#define LCD_ABC			0x00000008
#define LCD_IU0			0x00000010
#define LCD_IU1			0x00000020
#define LCD_OU			0x00000040
#define LCD_QD			0x00000080
#define LCD_EOF0		0x00000100
#define LCD_BS0			0x00000200
#define LCD_SINT			0x00000400
#define LCD_RD_ST		0x00000800
#define LCD_CMD_INTR	0x00001000
#define LCD_BER_CH(n)	(((n) & 0x7FFFFFFF) >> 28)

//
// LCD Controller Status Register (LCSR1)
//
#define LCD_SOF1	0x00000001
#define LCD_SOF2	0x00000002
#define LCD_SOF3	0x00000004
#define LCD_SOF4	0x00000008
#define LCD_SOF5	0x00000010
#define LCD_SOF6	0x00000020
#define LCD_EOF1	0x00000100
#define LCD_EOF2	0x00000200
#define LCD_EOF3	0x00000400
#define LCD_EOF4	0x00000800
#define LCD_EOF5	0x00001000
#define LCD_EOF6	0x00002000
#define LCD_BS1		0x00010000
#define LCD_BS2		0x00020000
#define LCD_BS3		0x00040000
#define LCD_BS4		0x00080000
#define LCD_BS5		0x00100000
#define LCD_BS6		0x00200000
#define LCD_IU2		0x02000000
#define LCD_IU3		0x04000000
#define LCD_IU4		0x08000000
#define LCD_IU5		0x10000000
#define LCD_IU6		0x20000000

//
// CLKEN register reserved and valid bits
//
#define XLLP_CLKEN_RESERVED_BITS  0xfc000000
#define XLLP_CLKEN_MASK (~(XLLP_CLKEN_RESERVED_BITS))
#define CLK_SSP3 0x00000010
#define CLK_LCD  0x00010000
#define CLK_SRAM 0x00100000

#define LTM035A776C_PIXEL_CLOCK_FREQUENCY 810   // 9.10 MHz

// Use the following for PixelDataFormat values
#define PDFOR_00		0x0
#define PDFOR_01		0x1
#define PDFOR_10		0x2
#define PDFOR_11		0x3

#endif