lcd.h

intel pxa270的bootlader

#ifndef BLOB_PXA_LCD_H
#define BLOB_PXA_LCD_H


//#define __REG(x)	(*((volatile u32 *)(x)))

/*
 *  Clocks Manager Register
 */
#define CCCR		__REG(0x41300000)  /* Core Clock Configuration Register */
#define CKEN		__REG(0x41300004)  /* Clock Enable Register */
#define OSCC		__REG(0x41300008)  /* Oscillator Configuration Register */
#define CCSR		__REG(0x4130000C)  /* Core Clock Status Register */


#define CKEN16_LCD	     (1 << 16)		/* LCD Unit Clock Enable */
#define CKEN0_PWM0	     (1 << 0)		/* PWM0 Clock Enable */


/*
 * Pulse Width Modulator
 */

#define PWM_CTRL0		__REG(0x40B00000)  /* PWM 0 Control Register */
#define PWM_PWDUTY0	__REG(0x40B00004)  /* PWM 0 Duty Cycle Register */
#define PWM_PERVAL0	__REG(0x40B00008)  /* PWM 0 Period Control Register */

#define PWM_CTRL1		__REG(0x40C00000)  /* PWM 1Control Register */
#define PWM_PWDUTY1	__REG(0x40C00004)  /* PWM 1 Duty Cycle Register */
#define PWM_PERVAL1	__REG(0x40C00008)  /* PWM 1 Period Control Register */

/*
 * Handy function to set GPIO alternate functions
 */
#define GPIO_MD_MASK_NR		0x07f
#define GPIO_MD_MASK_DIR		0x080
#define GPIO_MD_MASK_FN		0x300

#define GPIO_ALT_FN_2_OUT		0x280
#define GPIO16_PWM0_MD		(16 | GPIO_ALT_FN_2_OUT)

//#define GPIO_bit(x)	(1 << ((x) & 0x1f))
//#define _reg_GPDR(x)		(*(volatile u32 *)(0x40E0000C + ((x) & 0x60) >> 3))	//__REG2(0x40E0000C, ((x) & 0x60) >> 3)
//#define _reg_GAFR(x)		(*(volatile u32 *)(0x40E00054 + ((x) & 0x70) >> 3))	//__REG2(0x40E00054, ((x) & 0x70) >> 2)

/*
 * General Purpose I/O
 */

#define GPLR0		__REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
#define GPLR1		__REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
#define GPLR2		__REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */

#define GPDR0		__REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
#define GPDR1		__REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
#define GPDR2		__REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */

#define GPSR0		__REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
#define GPSR1		__REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
#define GPSR2		__REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<80:64> */

#define GPCR0		__REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
#define GPCR1		__REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
#define GPCR2		__REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <80:64> */

#define GRER0		__REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
#define GRER1		__REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
#define GRER2		__REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<80:64> */

#define GFER0		__REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
#define GFER1		__REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
#define GFER2		__REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<80:64> */

#define GEDR0		__REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
#define GEDR1		__REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
#define GEDR2		__REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */

#define GAFR0_L		__REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
#define GAFR0_U		__REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
#define GAFR1_L		__REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
#define GAFR1_U		__REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
#define GAFR2_L		__REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
#define GAFR2_U		__REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO 80 */

/*
 * LCD Controller
 */
#define LCCR0		__REG(0x44000000)  /* LCD Controller Control Register 0 */
#define LCCR1		__REG(0x44000004)  /* LCD Controller Control Register 1 */
#define LCCR2		__REG(0x44000008)  /* LCD Controller Control Register 2 */
#define LCCR3		__REG(0x4400000C)  /* LCD Controller Control Register 3 */
#define LCCR4		__REG(0x44000010)  /* LCD Controller Control Register 4 */
#define LCCR5		__REG(0x44000014)  /* LCD Controller Control Register 5 */

#define FBR0               __REG(0x44000020)  // DMA Channel 0 Frame Branch register
#define LCSR0		__REG(0x44000038)	//LCD Controller Status register 0
#define LCSR1		__REG(0x44000034)	//LCD Controller Status register 1


#define OVL1C1		__REG(0x44000050)  /* Overlay 1 Control Register 1 */
#define OVL1C2		__REG(0x44000060)  /* Overlay 1 Control Register 2 */
#define OVL2C1		__REG(0x44000070)  /* Overlay 2 Control Register 1 */
#define OVL2C2		__REG(0x44000080)  /* Overlay 2 Control Register 2 */
#define CCR			__REG(0x44000090)  /* Cursor Control Register */

#define FDADR0		__REG(0x44000200)  /* DMA Channel 0 Frame Descriptor Address Register */
#define FSADR0		__REG(0x44000204)  /* DMA Channel 0 Frame Source Address Register */
#define FIDR0		__REG(0x44000208)  /* DMA Channel 0 Frame ID Register */
#define LDCMD0		__REG(0x4400020C)  /* DMA Channel 0 Command Register */




#define OVL1C1_O1EN		(1<<31)		/* Enable bit for Overlay 1 */
#define OVL2C1_O2EN		(1<<31)		/* Enable bit for Overlay 2 */
#define CCR_CEN			(1<<31)		/* Enable bit for Cursor */


#define LCCR0_ENB		(1 << 0)		/* LCD Controller enable */
#define LCCR0_CMS		(1 << 1)		/* Color = 0, Monochrome = 1 */
#define LCCR0_SDS		(1 << 2)		/* Single Panel = 0, Dual Panel = 1 */
#define LCCR0_LDM		(1 << 3)		/* LCD Disable Done Mask */
#define LCCR0_SFM		(1 << 4)		/* Start of frame mask */
#define LCCR0_IUM		(1 << 5)		/* Input FIFO underrun mask */
#define LCCR0_EFM		(1 << 6)		/* End of Frame mask */
#define LCCR0_PAS		(1 << 7)		/* Passive = 0, Active = 1 */
//#define LCCR0_BLE		(1 << 8)		/* Little Endian = 0, Big Endian = 1 */
#define LCCR0_DPD		(1 << 9)		/* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */
#define LCCR0_DIS		(1 << 10)	/* LCD Disable */
#define LCCR0_QDM		(1 << 11)	/* LCD Quick Disable mask */
#define LCCR0_PDD		(0xff << 12)	/* Palette DMA request delay */
#define LCCR0_PDD_S		12
#define LCCR0_BM		(1 << 20) 	/* Branch mask */
#define LCCR0_OUM		(1 << 21)	/* Output FIFO underrun mask */
#define LCCR0_LCDT		(1 << 22)       /* LCD Panel Type */
#define LCCR0_RDSTM		(1 << 23)       /* Read Status Interrupt Mask */
#define LCCR0_CMDIM		(1 << 24)       /* Command Interrupt Mask */
#define LCCR0_OUC		(1 << 25)		/* Overlay Underlay Control Bit */

#define LCD_LCCR0		(LCCR0_OUC | LCCR0_CMDIM | LCCR0_RDSTM | \
                                 		LCCR0_OUM | LCCR0_BM | LCCR0_QDM | LCCR0_PAS | \
                                 		LCCR0_EFM | LCCR0_IUM | LCCR0_SFM | LCCR0_LDM)

#define LCCR3_HSP		(1 << 21)	/* horizontal sync polarity */
#define LCD_LCCR3 	       LCCR3_HSP

//#define LCD_BPP			16
/* PIXCLOCK --- unit 10khz*/
#define LCD_PIXCLOCK		521

#define LCD_XRES			320
#define LCD_YRES			240

#define LCD_HORIZONTAL_SYNC_PULSE_WIDTH		13
#define LCD_VERTICAL_SYNC_PULSE_WIDTH		2

#define LCD_BEGIN_OF_LINE_WAIT_COUNT			21
#define LCD_BEGIN_FRAME_WAIT_COUNT 			8

#define LCD_END_OF_LINE_WAIT_COUNT			11
#define LCD_END_OF_FRAME_WAIT_COUNT			5

#if 0
//#define LCCR1_PPL       Fld (10, 0)      /* Pixels Per Line - 1 */
#define LCCR1_DisWdth(Pixel)        (Pixel - 1)	/* Display Width [1..800 pix.]  */


//#define LCCR1_HSW       Fld (6, 10)     /* Horizontal Synchronization     */
#define LCCR1_HorSnchWdth(Tpix)      (Tpix << 10)   /* Horizontal Synchronization */   /* pulse Width [1..64 Tpix]  */ 
                        

//#define LCCR1_ELW       Fld (8, 16)     /* End-of-Line pixel clock Wait    */
#define LCCR1_EndLnDel(Tpix)       (Tpix << 16)      /*  End-of-Line Delay  */    /*  [1..256 Tpix] */
                       

//#define LCCR1_BLW       Fld (8, 24)     /* Beginning-of-Line pixel clock   */
#define LCCR1_BegLnDel(Tpix)          (Tpix << 24)  /*  Beginning-of-Line Delay */ /*  [1..256 Tpix]  */
                        

//#define LCCR2_LPP       Fld (10, 0)     /* Line Per Panel - 1  */
#define LCCR2_DisHght(Line)        (Line - 1)      /*  Display Height [1..1024 lines] */
                       

//#define LCCR2_VSW       Fld (6, 10)     /* Vertical Synchronization pulse  */  /* Width - 1 [Tln] (L_FCLK) */
#define LCCR2_VrtSnchWdth(Tln)      (Tln << 10)    /*  Vertical Synchronization pulse */  /*  Width [1..64 Tln]              */
                        

//#define LCCR2_EFW       Fld (8, 16)     /* End-of-Frame line clock Wait    */    /* count [Tln]   */
#define LCCR2_EndFrmDel(Tln)       (Tln << 16)      /*  End-of-Frame Delay  */  /*  [0..255 Tln]  */
                       

//#define LCCR2_BFW       Fld (8, 24)     /* Beginning-of-Frame line clock   */   /* Wait count [Tln]  */    
#define LCCR2_BegFrmDel(Tln)      (Tln << 24)      /*  Beginning-of-Frame Delay    */   /*  [0..255 Tln]   */ 
                        

//#define LCCR3_BPP       Fld (3, 24)     /* Bit Per Pixel */
#define LCCR3_Bpp(Bpp)          ((((Bpp & 0x7) << 24)) | (((Bpp & 0x8) << 26)))         /* Bit Per Pixel */
#endif

//#define DISPLAY_SDRAM_ADDR		(0xa0210000)

//#define DMA_DESC_SIZE               0x20
#define PALETTE_BUFFER_SIZE         0x400  // 1024
#define FRAME_BUFFER_SIZE           320*240*2
//#define DISPLAY_BUFFER_SIZE         0x2b0000


#define DISPLAY_BASE_PHYSICAL		0xa0210000	//0xA3A00000
//#define DISPLAY_BASE_VIRTUAL		io_p2v(DISPLAY_BASE_PHYSICAL)

#define DMA_CHANNEL_0_FRAME_DESCRIPTOR_BASE_PHYSICAL      DISPLAY_BASE_PHYSICAL
//#define DMA_CHANNEL_0_FRAME_DESCRIPTOR_BASE_VIRTUAL       (DISPLAY_BASE_VIRTUAL + 0)

//#define DMA_CHANNEL_1_FRAME_DESCRIPTOR_BASE_PHYSICAL      (DISPLAY_BASE_PHYSICAL + 0x20)
//#define DMA_CHANNEL_1_FRAME_DESCRIPTOR_BASE_VIRTUAL       (DISPLAY_BASE_VIRTUAL + 0x20)

//#define DMA_CHANNEL_0_ALT_FRAME_DESCRIPTOR_BASE_PHYSICAL  (DISPLAY_BASE_PHYSICAL + 0x20 + 0x20)
//#define DMA_CHANNEL_0_ALT_FRAME_DESCRIPTOR_BASE_VIRTUAL   (DISPLAY_BASE_VIRTUAL + 0x20 + 0x20)

//#define PALETTE_FRAME_DESCRIPTOR_BASE_PHYSICAL            (DISPLAY_BASE_PHYSICAL + 0x20 + 0x20 + 0x20)
//#define PALETTE_FRAME_DESCRIPTOR_BASE_VIRTUAL             (DISPLAY_BASE_VIRTUAL + 0x20 + 0x20 + 0x20)

//#define PALETTE_BUFFER_BASE_PHYSICAL                      (DISPLAY_BASE_PHYSICAL + 0x20 + 0x20 + 0x20 + 0x20)
//#define PALETTE_BUFFER_BASE_VIRTUAL                       (PALETTE_FRAME_DESCRIPTOR_BASE_VIRTUAL + 0x20)

#define FRAME_BUFFER_0_BASE_PHYSICAL     (DISPLAY_BASE_PHYSICAL + 0x480) 
															// 0xa0220480


#if 0
/* Bit Position Macros */
#define XLLP_BIT_0    (1 << 0)
#define XLLP_BIT_1    (1 << 1)
#define XLLP_BIT_2    (1 << 2)
#define XLLP_BIT_3    (1 << 3)
#define XLLP_BIT_4    (1 << 4)
#define XLLP_BIT_5    (1 << 5)
#define XLLP_BIT_6    (1 << 6)
#define XLLP_BIT_7    (1 << 7)
#define XLLP_BIT_8    (1 << 8)
#define XLLP_BIT_9    (1 << 9)
#define XLLP_BIT_10   (1 << 10)
#define XLLP_BIT_11   (1 << 11)
#define XLLP_BIT_12   (1 << 12)
#define XLLP_BIT_13   (1 << 13)
#define XLLP_BIT_14   (1 << 14)
#define XLLP_BIT_15   (1 << 15)
#define XLLP_BIT_16   (1 << 16)
#define XLLP_BIT_17   (1 << 17)
#define XLLP_BIT_18   (1 << 18)
#define XLLP_BIT_19   (1 << 19)
#define XLLP_BIT_20   (1 << 20)
#define XLLP_BIT_21   (1 << 21)
#define XLLP_BIT_22   (1 << 22)
#define XLLP_BIT_23   (1 << 23)
#define XLLP_BIT_24   (1 << 24)
#define XLLP_BIT_25   (1 << 25)