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<html><head><title>饮水思源精华区</title><Content-type: text/html; charset=gb2312><link rel=stylesheet type=text/css href="bbsdl.css"></head><table cellspacing=0 class=title width=90%><th class=title align=left width=20%>饮水思源站</th><th class=title align=center width=60%>文章阅读</th><th class=title align=right width=20%>精华区离线浏览</th></tr></table><hr><table align=center cellspacing=1 class=doc><tr><td>发信人: xozhao (XO), 信区: DSP<br>标 题: 谈谈其他DSP(1)Motorola<br>发信站: 饮水思源站 (Sat Jun 19 12:48:38 1999) , 转信<br>其他公司的DSP也是各有特色的嘛,<br>Motorola 的24位运算宽度使你不在为精度不够而烦恼<br><br>DSP56001:<br>主频: 20.5, 27, or 33 MHz<br>位数: 24-bit fixed point DSP<br> 24 bit data bus, 16 bit address bus, <br> 56 bit accumulators (2)<br>外设: host interface port,<br> serial ports (2), <br> general purpose I/O pins, timer.<br>内存: Harvard architecture. <br> 512 words program RAM, 32 words bootstrap ROM, <br> 512 words data RAM, 512 words data ROM on chip. <br>封装: PGA, CQFP or PQFP packaging.<br><br>DSP56000: <br>Mask-programmed version of DSP56001, same peripherals and<br>data memories, 3.75k words program ROM on chip.<br><br>DSP56002:<br>特点:--- based on new 24-bit DSP56k core<br> --- a superset of the DSP56001 architecture<br> --- with On-Chip Emulation (OnCE) debug port,<br> --- clock PLL and improved bus arbitration<br> --- four cycle double precision multiply<br> --- support for block floating point<br> --- Same memory as in DSP56001,<br> except for 64 words bootstrap ROM. <br><br>主频: 40MHz<br>外设: Host interface port<br> serial ports (2),<br> general purpose I/O pins,<br> programmable 24-bit timer,<br> non-maskable interrupt<br>封装: PGA and CQFP packaging.<br><br>DSP56L002:<br>Low-power version of the DSP56002 offering identical<br>performance as the DSP56002 but at 3.3V.<br>封装: PQFP.<br><br>DSP56004:<br>特点: modular DSP, same 24-bit DSP56k core as in DSP56002.<br> Targeted to consumer digital audio applications<br>外设: On-Chip Emulation (OnCE) debug port<br> clock PLL, serial host interface (I2C and SPI)<br> four general purpose I/O pins,<br> two stereo serial audio receivers (I2S/Sony)<br> three stereo serial audio transmitters (I2S/Sony)<br> external SRAM/DRAM memory interface with 8-bit <br> data bus.<br>主频: 40 MHz (5V supply) in 80-pin QFP package.<br><br>DSP96002:<br>核: IEEE format floating point DSP;<br> two complete 32 bit data and address buses;<br> Harvard architecture. <br>内存:1k words program RAM,<br> 64 words bootstrap ROM,<br> 1k words data RAM, <br> 1k words data ROM,<br>主频: Available in 33 MHz or 40 MHz<br>封装: 223-pin PGA packaging.<br>--<br>※ 来源:·饮水思源站 bbs.sjtu.edu.cn·[FROM: www-post@bbs]<br></tr></table><br><caption align=bottom><hr><table align=center cellspacing=1 class=foot><tr><td class=foot><a href="a-2.htm">返回</tr></table><p class=copyr align=center>Copyright © 2001 <a class=copyr href="http://bbs.sjtu.edu.cn">SJTUBBS</a>, All Rights Reserved.<br><br>版权所有<a class=copyr href="telnet://bbs.sjtu.edu.cn">上海交大BBS饮水思源站</a></caption></body></html>
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