gfx_regs.h

DirectFB-1.0.1可用于linux的嵌入式GUI

/* ALPHA COLOR BIT DEFINITION (REGISTERS 0x68, 0x78, AND 0x88) */

#define RCDF_ALPHA_COLOR_ENABLE           0x01000000

/* ALPHA CONTROL BIT DEFINITIONS (REGISTERS 0x6C, 0x7C, AND 0x8C) */

#define RCDF_ACTRL_WIN_ENABLE				0x00010000
#define RCDF_ACTRL_LOAD_ALPHA				0x00020000

/* VIDEO REQUEST DEFINITIONS (REGISTER 0x90) */

#define RCDF_VIDEO_Y_REQUEST_POS          0
#define RCDF_VIDEO_X_REQUEST_POS          16
#define RCDF_VIDEO_REQUEST_MASK           0x000007FF

/* GEODELINK DEVICE MSR REGISTER SUMMARY */

#define MBD_MSR_CAP         0x2000   /* Device Capabilities                   */
#define MBD_MSR_CONFIG      0x2001   /* Device Master Configuration Register  */
#define MBD_MSR_SMI         0x2002   /* MBus Device SMI Register              */
#define MBD_MSR_ERROR       0x2003   /* MBus Device Error                     */
#define MBD_MSR_PM          0x2004   /* MBus Device Power Management Register */
#define MBD_MSR_DIAG        0x2005   /* Mbus Device Diagnostic Register       */

/* DISPLAY FILTER MBD_MSR_DIAG DEFINITIONS */

#define RCDF_MBD_DIAG_SEL0        0x00007FFF /* Lower 32-bits of Diag Bus Select     */
#define RCDF_MBD_DIAG_EN0         0x00008000 /* Enable for lower 32-bits of diag bus */
#define RCDF_MBD_DIAG_SEL1        0x7FFF0000 /* Upper 32-bits of Diag Bus Select     */
#define RCDF_MBD_DIAG_EN1         0x80000000 /* Enable for upper 32-bits of diag bus */

/* DISPLAY FILTER MBD_MSR_CONFIG DEFINITIONS */

#define RCDF_CONFIG_FMT_MASK      0x00000038 /* Output Format */
#define RCDF_CONFIG_FMT_CRT       0x00000000
#define RCDF_CONFIG_FMT_FP        0x00000008 

/* MCP MSR DEFINITIONS */

#define MCP_CLKOFF                0x0010
#define MCP_CLKACTIVE             0x0011
#define MCP_CLKDISABLE            0x0012
#define MCP_CLK4ACK               0x0013
#define MCP_SYS_RSTPLL            0x0014
#define MCP_DOTPLL                0x0015
#define MCP_DBGCLKCTL             0x0016
#define MCP_RC_REVID              0x0017
#define MCP_SETM0CTL              0x0040
#define MCP_SETN0CTL              0x0048
#define MCP_CMPVAL0               0x0050
#define MCP_CMPMASK0              0x0051
#define MCP_REGA                  0x0058
#define MCP_REGB                  0x0059
#define MCP_REGAMASK              0x005A
#define MCP_REGAVAL               0x005B
#define MCP_REGBMASK              0x005C
#define MCP_REGBVAL               0x005D
#define MCP_FIFOCTL               0x005E
#define MCP_DIAGCTL               0x005F
#define MCP_H0CTL                 0x0060
#define MCP_XSTATE                0x0066
#define MCP_YSTATE                0x0067
#define MCP_ACTION0               0x0068

/* MCP_SYS_RSTPLL DEFINITIONS */

#define MCP_DOTPOSTDIV3           0x00000008
#define MCP_DOTPREMULT2           0x00000004
#define MCP_DOTPREDIV2            0x00000002

/* MCP MBD_MSR_DIAG DEFINITIONS */

#define MCP_MBD_DIAG_SEL0         0x00000007
#define MCP_MBD_DIAG_EN0          0x00008000
#define MCP_MBD_DIAG_SEL1         0x00070000
#define MCP_MBD_DIAG_EN1          0x80000000

/* MCP_DOTPLL DEFINITIONS */

#define MCP_DOTPLL_P              0x00000003
#define MCP_DOTPLL_N              0x000001FC
#define MCP_DOTPLL_M              0x00001E00
#define MCP_DOTPLL_LOCK           0x02000000
#define MCP_DOTPLL_BYPASS         0x00008000


/*---------------------------------------------------*/
/*  THIRD GENERATION DISPLAY CONTROLLER (CASTLE)     */
/*---------------------------------------------------*/

#define DC3_UNLOCK              0x00000000  /* Unlock register               */
#define DC3_GENERAL_CFG         0x00000004  /* Config registers              */
#define DC3_DISPLAY_CFG         0x00000008  

#define DC3_FB_ST_OFFSET        0x00000010  /* Frame buffer start offset     */
#define DC3_CB_ST_OFFSET        0x00000014  /* Compression start offset      */
#define DC3_CURS_ST_OFFSET      0x00000018  /* Cursor buffer start offset    */
#define DC3_VID_Y_ST_OFFSET     0x00000020  /* Video Y Buffer start offset   */
#define DC3_VID_U_ST_OFFSET     0x00000024  /* Video U Buffer start offset   */
#define DC3_VID_V_ST_OFFSET     0x00000028  /* Video V Buffer start offset   */
#define DC3_LINE_SIZE           0x00000030  /* Video, CB, and FB line sizes  */
#define DC3_GFX_PITCH           0x00000034  /* FB and DB skip counts         */
#define DC3_VID_YUV_PITCH       0x00000038  /* Y, U and V buffer skip counts */

#define DC3_H_ACTIVE_TIMING     0x00000040  /* Horizontal timings            */
#define DC3_H_BLANK_TIMING      0x00000044
#define DC3_H_SYNC_TIMING       0x00000048
#define DC3_V_ACTIVE_TIMING     0x00000050  /* Vertical Timings              */
#define DC3_V_BLANK_TIMING      0x00000054
#define DC3_V_SYNC_TIMING       0x00000058

#define DC3_CURSOR_X            0x00000060  /* Cursor X position             */
#define DC3_CURSOR_Y            0x00000064  /* Cursor Y Position             */
#define DC3_LINE_CNT_STATUS     0x0000006C  /* Icon Y Position               */

#define DC3_PAL_ADDRESS         0x00000070  /* Palette Address               */
#define DC3_PAL_DATA            0x00000074  /* Palette Data                  */
#define DC3_DFIFO_DIAG          0x00000078  /* Display FIFO diagnostic       */
#define DC3_CFIFO_DIAG          0x0000007C  /* Compression FIFO diagnostic   */

#define DC3_VID_DS_DELTA        0x00000080  /* Vertical Downscaling fraction */

#define DC3_PHY_MEM_OFFSET      0x00000084  /* VG Base Address Register      */
#define DC3_DV_CTL              0x00000088  /* Dirty-Valid Control Register  */
#define DC3_DV_ACC              0x0000008C  /* Dirty-Valid RAM Access        */

#define DC3_COLOR_KEY           0x000000B8  /* Graphics color key            */
#define DC3_COLOR_MASK          0x000000BC  /* Graphics color key mask       */

/* UNLOCK VALUE */

#define DC3_UNLOCK_VALUE		0x00004758		/* used to unlock DC regs	*/

/* VG MBUS DEVICE SMI MSR FIELDS */

#define DC3_VG_BL_MASK            0x00000001
#define DC3_MISC_MASK             0x00000002
#define DC3_ISR0_MASK             0x00000004
#define DC3_VGA_BL_MASK           0x00000008
#define DC3_CRTCIO_MSK            0x00000010
#define DC3_VG_BLANK_SMI          0x00000001
#define DC3_MISC_SMI              0x00000002
#define DC3_ISR0_SMI              0x00000004
#define DC3_VGA_BLANK_SMI         0x00000008
#define DC3_CRTCIO_SMI            0x00000010

/* DC3_GENERAL_CFG BIT FIELDS */

#define DC3_GCFG_DBUG             0x80000000
#define DC3_GCFG_DBSL             0x40000000
#define DC3_GCFG_CFRW             0x20000000
#define DC3_GCFG_DIAG             0x10000000
#define DC3_GCFG_GXRFS4           0x08000000
#define DC3_GCFG_SGFR             0x04000000
#define DC3_GCFG_SGRE             0x02000000
#define DC3_GCFG_SIGE             0x01000000
#define DC3_GCFG_YUVM             0x00100000
#define DC3_GCFG_VDSE             0x00080000
#define DC3_GCFG_VGAFT            0x00040000
#define DC3_GCFG_FDTY             0x00020000
#define DC3_GCFG_STFM             0x00010000
#define DC3_GCFG_DFHPEL_MASK      0x0000F000
#define DC3_GCFG_DFHPSL_MASK      0x00000F00
#define DC3_GCFG_VGAE             0x00000080
#define DC3_GCFG_DECE             0x00000040
#define DC3_GCFG_CMPE             0x00000020
#define DC3_GCFG_VIDE             0x00000008
#define DC3_GCFG_ICNE             0x00000004
#define DC3_GCFG_CURE             0x00000002
#define DC3_GCFG_DFLE             0x00000001

/* DC3_DISPLAY_CFG BIT FIELDS */

#define DC3_DCFG_A20M             0x80000000
#define DC3_DCFG_A18M             0x40000000
#define DC3_DCFG_VISL             0x08000000
#define DC3_DCFG_FRLK             0x04000000
#define DC3_DCFG_PALB             0x02000000
#define DC3_DCFG_PIX_PAN_MASK     0x00F00000
#define DC3_DCFG_DCEN             0x00080000
#define DC3_DCFG_16BPP_MODE_MASK  0x00000C00
#define DC3_DCFG_16BPP            0x00000000        
#define DC3_DCFG_15BPP            0x00000400
#define DC3_DCFG_12BPP            0x00000800
#define DC3_DCFG_DISP_MODE_MASK   0x00000300
#define DC3_DCFG_DISP_MODE_8BPP   0x00000000
#define DC3_DCFG_DISP_MODE_16BPP  0x00000100
#define DC3_DCFG_DISP_MODE_24BPP  0x00000200
#define DC3_DCFG_SCLE             0x00000080
#define DC3_DCFG_TRUP             0x00000040
#define DC3_DCFG_VIEN             0x00000020
#define DC3_DCFG_VDEN             0x00000010
#define DC3_DCFG_GDEN             0x00000008
#define DC3_DCFG_VCKE             0x00000004
#define DC3_DCFG_PCKE             0x00000002
#define DC3_DCFG_TGEN             0x00000001

/* DC3_LINE_CNT BIT FIELDS     */

#define DC3_LNCNT_DNA             0x80000000
#define DC3_LNCNT_VNA             0x40000000
#define DC3_LNCNT_VSA             0x20000000
#define DC3_LNCNT_VINT            0x10000000
#define DC3_LNCNT_FLIP            0x08000000
#define DC3_LNCNT_V_LINE_CNT      0x07FF0000
#define DC3_LNCNT_VFLIP           0x00008000
#define DC3_LNCNT_SIGC            0x00004000
#define DC3_LNCNT_SS_LINE_CMP     0x000007FF

/* DC3_FB_ST_OFFSET BIT FIELDS */

#define DC3_FB_ST_OFFSET_MASK     0x0FFFFFFF

/* DC3_CB_ST_OFFSET BIT FIELDS */

#define DC3_CB_ST_OFFSET_MASK     0x0FFFFFFF

/* DC3_CURS_ST_OFFSET BIT FIELDS */

#define DC3_CURS_ST_OFFSET_MASK   0x0FFFFFFF

/* DC3_ICON_ST_OFFSET BIT FIELDS */

#define DC3_ICON_ST_OFFSET_MASK   0x0FFFFFFF

/* DC3_VID_Y_ST_OFFSET BIT FIELDS */

#define DC3_VID_Y_ST_OFFSET_MASK  0x0FFFFFFF

/* DC3_VID_U_ST_OFFSET BIT FIELDS */

#define DC3_VID_U_ST_OFFSET_MASK  0x0FFFFFFF

/* DC3_VID_V_ST_OFFSET BIT FIELDS */

#define DC3_VID_V_ST_OFFSET_MASK  0x0FFFFFFF

/* DC3_LINE_SIZE BIT FIELDS */

#define DC3_LINE_SIZE_VLS_MASK    0x3FF00000
#define DC3_LINE_SIZE_CBLS_MASK   0x0007F000
#define DC3_LINE_SIZE_FBLS_MASK   0x000003FF
#define DC3_LINE_SIZE_CB_SHIFT    12
#define DC3_LINE_SIZE_VB_SHIFT    20

/* DC3_GFX_PITCH BIT FIELDS */

#define DC3_GFX_PITCH_CBP_MASK    0xFFFF0000
#define DC3_GFX_PITCH_FBP_MASK    0x0000FFFF

/* DC3_VID_YUV_PITCH BIT FIELDS */

#define DC3_YUV_PITCH_UVP_MASK    0xFFFF0000
#define DC3_YUV_PITCH_YBP_MASK    0x0000FFFF

/* DC3_H_ACTIVE_TIMING BIT FIELDS */

#define DC3_HAT_HT_MASK           0x0FF80000
#define DC3_HAT_HA_MASK           0x00000FF8

/* DC3_H_BLANK_TIMING BIT FIELDS */

#define DC3_HBT_HBE_MASK          0x0FF80000
#define DC3_HBT_HBS_MASK          0x00000FF8

/* DC3_H_SYNC_TIMING BIT FIELDS */

#define DC3_HST_HSE_MASK          0x0FF80000
#define DC3_HST_HSS_MASK          0x00000FF8 

/* DC3_V_ACTIVE_TIMING BIT FIELDS */

#define DC3_VAT_VT_MASK           0x07FF0000
#define DC3_VAT_VA_MASK           0x000007FF

/* DC3_V_BLANK_TIMING BIT FIELDS */

#define DC3_VBT_VBE_MASK          0x07FF0000
#define DC3_VBT_VBS_MASK          0x000007FF

/* DC3_V_SYNC_TIMING BIT FIELDS */

#define DC3_VST_VSE_MASK          0x07FF0000
#define DC3_VST_VSS_MASK          0x000007FF 

/* DC3_DV_CTL BIT DEFINITIONS */

#define DC3_DV_LINE_SIZE_MASK     0x00000C00
#define DC3_DV_LINE_SIZE_1024     0x00000000
#define DC3_DV_LINE_SIZE_2048     0x00000400
#define DC3_DV_LINE_SIZE_4096     0x00000800
#define DC3_DV_LINE_SIZE_8192     0x00000C00

#define DC3_CLR_KEY_DATA_MASK     0x00FFFFFF
#define DC3_CLR_KEY_ENABLE        0x01000000
#define DC3_CLR_KEY_INVERT        0x02000000

/* VGA DEFINITIONS */

#define DC3_SEQUENCER_INDEX       0x03C4
#define DC3_SEQUENCER_DATA        0x03C5
#define DC3_SEQUENCER_RESET       0x00
#define DC3_SEQUENCER_CLK_MODE    0x01

#define DC3_RESET_VGA_DISP_ENABLE 0x03
#define DC3_CLK_MODE_SCREEN_OFF   0x20

/*---------------------------------------------------*/
/*  CASTLE DISPLAY FILTER                          */
/*---------------------------------------------------*/

/* CASTLE VIDEO REGISTER DEFINITIONS */

#define CASTLE_VIDEO_CONFIG 				    0x000
#define CASTLE_DISPLAY_CONFIG				    0x008
#define CASTLE_VIDEO_X_POS						0x010
#define CASTLE_VIDEO_Y_POS						0x018
#define CASTLE_VIDEO_COLOR_KEY					0x028
#define CASTLE_VIDEO_COLO