gfx_regs.h

DirectFB-1.0.1可用于linux的嵌入式GUI

#define MDC_V_BLANK_TIMING      0x00000054
#define MDC_V_SYNC_TIMING       0x00000058

#define MDC_CURSOR_X            0x00000060  /* Cursor X position             */
#define MDC_CURSOR_Y            0x00000064  /* Cursor Y Position             */
#define MDC_ICON_X              0x00000068  /* Icon X Position               */
#define MDC_LINE_CNT_STATUS     0x0000006C  /* Icon Y Position               */

#define MDC_PAL_ADDRESS         0x00000070  /* Palette Address               */
#define MDC_PAL_DATA            0x00000074  /* Palette Data                  */
#define MDC_DFIFO_DIAG          0x00000078  /* Display FIFO diagnostic       */
#define MDC_CFIFO_DIAG          0x0000007C  /* Compression FIFO diagnostic   */

#define MDC_VID_DS_DELTA        0x00000080  /* Vertical Downscaling fraction */

#define MDC_PHY_MEM_OFFSET      0x00000084  /* VG Base Address Register      */
#define MDC_DV_CTL              0x00000088  /* Dirty-Valid Control Register  */
#define MDC_DV_ACC              0x0000008C  /* Dirty-Valid RAM Access        */

/* UNLOCK VALUE */

#define MDC_UNLOCK_VALUE		0x00004758		/* used to unlock DC regs	*/

/* VG MBUS DEVICE SMI MSR FIELDS */

#define MDC_VG_BL_MASK            0x00000001
#define MDC_MISC_MASK             0x00000002
#define MDC_ISR0_MASK             0x00000004
#define MDC_VGA_BL_MASK           0x00000008
#define MDC_CRTCIO_MSK            0x00000010
#define MDC_VG_BLANK_SMI          0x00000001
#define MDC_MISC_SMI              0x00000002
#define MDC_ISR0_SMI              0x00000004
#define MDC_VGA_BLANK_SMI         0x00000008
#define MDC_CRTCIO_SMI            0x00000010

/* MDC_GENERAL_CFG BIT FIELDS */

#define MDC_GCFG_DBUG             0x80000000
#define MDC_GCFG_DBSL             0x40000000
#define MDC_GCFG_CFRW             0x20000000
#define MDC_GCFG_DIAG             0x10000000
#define MDC_GCFG_GXRFS4           0x08000000
#define MDC_GCFG_SGFR             0x04000000
#define MDC_GCFG_SGRE             0x02000000
#define MDC_GCFG_SIGE             0x01000000
#define MDC_GCFG_YUVM             0x00100000
#define MDC_GCFG_VDSE             0x00080000
#define MDC_GCFG_VGAFT            0x00040000
#define MDC_GCFG_FDTY             0x00020000
#define MDC_GCFG_STFM             0x00010000
#define MDC_GCFG_DFHPEL_MASK      0x0000F000
#define MDC_GCFG_DFHPSL_MASK      0x00000F00
#define MDC_GCFG_VGAE             0x00000080
#define MDC_GCFG_DECE             0x00000040
#define MDC_GCFG_CMPE             0x00000020
#define MDC_GCFG_VIDE             0x00000008
#define MDC_GCFG_ICNE             0x00000004
#define MDC_GCFG_CURE             0x00000002
#define MDC_GCFG_DFLE             0x00000001

/* MDC_DISPLAY_CFG BIT FIELDS */

#define MDC_DCFG_A20M             0x80000000
#define MDC_DCFG_A18M             0x40000000
#define MDC_DCFG_VISL             0x08000000
#define MDC_DCFG_FRLK             0x04000000
#define MDC_DCFG_PALB             0x02000000
#define MDC_DCFG_PIX_PAN_MASK     0x00F00000
#define MDC_DCFG_DCEN             0x00080000
#define MDC_DCFG_16BPP_MODE_MASK  0x00000C00
#define MDC_DCFG_16BPP            0x00000000        
#define MDC_DCFG_15BPP            0x00000400
#define MDC_DCFG_12BPP            0x00000800
#define MDC_DCFG_DISP_MODE_MASK   0x00000300
#define MDC_DCFG_DISP_MODE_8BPP   0x00000000
#define MDC_DCFG_DISP_MODE_16BPP  0x00000100
#define MDC_DCFG_DISP_MODE_24BPP  0x00000200
#define MDC_DCFG_SCLE             0x00000080
#define MDC_DCFG_TRUP             0x00000040
#define MDC_DCFG_VIEN             0x00000020
#define MDC_DCFG_VDEN             0x00000010
#define MDC_DCFG_GDEN             0x00000008
#define MDC_DCFG_VCKE             0x00000004
#define MDC_DCFG_PCKE             0x00000002
#define MDC_DCFG_TGEN             0x00000001

/* MDC_LINE_CNT BIT FIELDS     */

#define MDC_LNCNT_DNA             0x80000000
#define MDC_LNCNT_VNA             0x40000000
#define MDC_LNCNT_VSA             0x20000000
#define MDC_LNCNT_VINT            0x10000000
#define MDC_LNCNT_FLIP            0x08000000
#define MDC_LNCNT_V_LINE_CNT      0x07FF0000
#define MDC_LNCNT_VFLIP           0x00008000
#define MDC_LNCNT_SIGC            0x00004000
#define MDC_LNCNT_SS_LINE_CMP     0x000007FF

/* MDC_FB_ST_OFFSET BIT FIELDS */

#define MDC_FB_ST_OFFSET_MASK     0x0FFFFFFF

/* MDC_CB_ST_OFFSET BIT FIELDS */

#define MDC_CB_ST_OFFSET_MASK     0x0FFFFFFF

/* MDC_CURS_ST_OFFSET BIT FIELDS */

#define MDC_CURS_ST_OFFSET_MASK   0x0FFFFFFF

/* MDC_ICON_ST_OFFSET BIT FIELDS */

#define MDC_ICON_ST_OFFSET_MASK   0x0FFFFFFF

/* MDC_VID_Y_ST_OFFSET BIT FIELDS */

#define MDC_VID_Y_ST_OFFSET_MASK  0x0FFFFFFF

/* MDC_VID_U_ST_OFFSET BIT FIELDS */

#define MDC_VID_U_ST_OFFSET_MASK  0x0FFFFFFF

/* MDC_VID_V_ST_OFFSET BIT FIELDS */

#define MDC_VID_V_ST_OFFSET_MASK  0x0FFFFFFF

/* MDC_LINE_SIZE BIT FIELDS */

#define MDC_LINE_SIZE_VLS_MASK    0xFF000000
#define MDC_LINE_SIZE_CBLS_MASK   0x007F0000
#define MDC_LINE_SIZE_FBLS_MASK   0x000007FF

/* MDC_GFX_PITCH BIT FIELDS */

#define MDC_GFX_PITCH_CBP_MASK    0xFFFF0000
#define MDC_GFX_PITCH_FBP_MASK    0x0000FFFF

/* MDC_VID_YUV_PITCH BIT FIELDS */

#define MDC_YUV_PITCH_UVP_MASK    0xFFFF0000
#define MDC_YUV_PITCH_YBP_MASK    0x0000FFFF

/* MDC_H_ACTIVE_TIMING BIT FIELDS */

#define MDC_HAT_HT_MASK           0x0FF80000
#define MDC_HAT_HA_MASK           0x00000FF8

/* MDC_H_BLANK_TIMING BIT FIELDS */

#define MDC_HBT_HBE_MASK          0x0FF80000
#define MDC_HBT_HBS_MASK          0x00000FF8

/* MDC_H_SYNC_TIMING BIT FIELDS */

#define MDC_HST_HSE_MASK          0x0FF80000
#define MDC_HST_HSS_MASK          0x00000FF8 

/* MDC_V_ACTIVE_TIMING BIT FIELDS */

#define MDC_VAT_VT_MASK           0x07FF0000
#define MDC_VAT_VA_MASK           0x000007FF

/* MDC_V_BLANK_TIMING BIT FIELDS */

#define MDC_VBT_VBE_MASK          0x07FF0000
#define MDC_VBT_VBS_MASK          0x000007FF

/* MDC_V_SYNC_TIMING BIT FIELDS */

#define MDC_VST_VSE_MASK          0x07FF0000
#define MDC_VST_VSS_MASK          0x000007FF 

/* MDC_DV_CTL BIT DEFINITIONS */

#define MDC_DV_LINE_SIZE_MASK     0x00000C00
#define MDC_DV_LINE_SIZE_1024     0x00000000
#define MDC_DV_LINE_SIZE_2048     0x00000400
#define MDC_DV_LINE_SIZE_4096     0x00000800
#define MDC_DV_LINE_SIZE_8192     0x00000C00

/* VGA DEFINITIONS */

#define MDC_SEQUENCER_INDEX       0x03C4
#define MDC_SEQUENCER_DATA        0x03C5
#define MDC_SEQUENCER_RESET       0x00
#define MDC_SEQUENCER_CLK_MODE    0x01

#define MDC_RESET_VGA_DISP_ENABLE 0x03
#define MDC_CLK_MODE_SCREEN_OFF   0x20


/*---------------------------------------------------*/
/*  REDCLOUD DISPLAY FILTER                          */
/*---------------------------------------------------*/

/* RCDF VIDEO REGISTER DEFINITIONS */

#define RCDF_VIDEO_CONFIG 				    0x000
#define RCDF_DISPLAY_CONFIG				    0x008
#define RCDF_VIDEO_X_POS					0x010
#define RCDF_VIDEO_Y_POS					0x018
#define RCDF_VIDEO_SCALE					0x020
#define RCDF_VIDEO_COLOR_KEY				0x028
#define RCDF_VIDEO_COLOR_MASK				0x030
#define RCDF_PALETTE_ADDRESS 				0x038
#define RCDF_PALETTE_DATA	 				0x040
#define RCDF_VID_MISC						0x050
#define RCDF_VID_CLOCK_SELECT				0x058
#define RCDF_VIDEO_DOWNSCALER_CONTROL       0x078 
#define RCDF_VIDEO_DOWNSCALER_COEFFICIENTS  0x080  
#define RCDF_VID_CRC						0x088
#define RCDF_VID_CRC32						0x090
#define RCDF_VID_ALPHA_CONTROL			    0x098
#define RCDF_CURSOR_COLOR_KEY				0x0A0
#define RCDF_CURSOR_COLOR_MASK			    0x0A8
#define RCDF_CURSOR_COLOR_1				    0x0B0
#define RCDF_CURSOR_COLOR_2				    0x0B8
#define RCDF_ALPHA_XPOS_1					0x0C0
#define RCDF_ALPHA_YPOS_1					0x0C8
#define RCDF_ALPHA_COLOR_1				    0x0D0
#define RCDF_ALPHA_CONTROL_1				0x0D8
#define RCDF_ALPHA_XPOS_2					0x0E0
#define RCDF_ALPHA_YPOS_2					0x0E8
#define RCDF_ALPHA_COLOR_2				    0x0F0
#define RCDF_ALPHA_CONTROL_2				0x0F8
#define RCDF_ALPHA_XPOS_3					0x100
#define RCDF_ALPHA_YPOS_3					0x108
#define RCDF_ALPHA_COLOR_3				    0x110
#define RCDF_ALPHA_CONTROL_3				0x118
#define RCDF_VIDEO_REQUEST                  0x120
#define RCDF_ALPHA_WATCH                    0x128
#define RCDF_VIDEO_TEST_MODE                0x210
#define RCDF_POWER_MANAGEMENT               0x410

/* DISPLAY FILTER POWER MANAGEMENT DEFINITIONS */

#define RCDF_PM_PANEL_POWER_ON              0x01000000

/* DISPLAY FILTER MSRS */

#define RCDF_MBD_MSR_DIAG_DF				0x2010
#define RCDF_DIAG_32BIT_CRC					0x80000000

/* "RCDF_VIDEO_CONFIG" BIT DEFINITIONS */

#define RCDF_VCFG_VID_EN					0x00000001	
#define RCDF_VCFG_VID_INP_FORMAT			0x0000000C	
#define RCDF_VCFG_X_FILTER_EN				0x00000040	
#define RCDF_VCFG_Y_FILTER_EN				0x00000080	
#define RCDF_VCFG_LINE_SIZE_LOWER_MASK	    0x0000FF00	
#define RCDF_VCFG_INIT_READ_MASK			0x01FF0000	
#define RCDF_VCFG_LINE_SIZE_UPPER			0x08000000	
#define RCDF_VCFG_4_2_0_MODE				0x10000000	
#define RCDF_VCFG_UYVY_FORMAT				0x00000000
#define RCDF_VCFG_Y2YU_FORMAT				0x00000004
#define RCDF_VCFG_YUYV_FORMAT				0x00000008
#define RCDF_VCFG_YVYU_FORMAT				0x0000000C

/* "RCDF_DISPLAY_CONFIG" BIT DEFINITIONS */

#define RCDF_DCFG_DIS_EN				    0x00000001	
#define RCDF_DCFG_HSYNC_EN				    0x00000002	
#define RCDF_DCFG_VSYNC_EN				    0x00000004	
#define RCDF_DCFG_DAC_BL_EN				    0x00000008	
#define RCDF_DCFG_FP_PWR_EN				    0x00000040
#define RCDF_DCFG_FP_DATA_EN				0x00000080	
#define RCDF_DCFG_CRT_HSYNC_POL 			0x00000100	
#define RCDF_DCFG_CRT_VSYNC_POL 			0x00000200		
#define RCDF_DCFG_CRT_SYNC_SKW_MASK		    0x0001C000
#define RCDF_DCFG_CRT_SYNC_SKW_INIT		    0x00010000
#define RCDF_DCFG_PWR_SEQ_DLY_MASK		    0x000E0000
#define RCDF_DCFG_PWR_SEQ_DLY_INIT		    0x00080000
#define RCDF_DCFG_VG_CK					    0x00100000
#define RCDF_DCFG_GV_PAL_BYP				0x00200000
#define RCDF_DAC_VREF                       0x04000000
#define RCDF_FP_ON_STATUS                   0x08000000

/* "RCDF_VID_MISC" BIT DEFINITIONS */

#define RCDF_GAMMA_BYPASS_BOTH              0x00000001
#define RCDF_DAC_POWER_DOWN                 0x00000400
#define RCDF_ANALOG_POWER_DOWN              0x00000800

/* "RCDF_VIDEO_DOWNSCALER_CONTROL" BIT DEFINITIONS */

#define RCDF_VIDEO_DOWNSCALE_ENABLE         0x00000001
#define RCDF_VIDEO_DOWNSCALE_FACTOR_POS     1
#define RCDF_VIDEO_DOWNSCALE_FACTOR_MASK    0x0000001E
#define RCDF_VIDEO_DOWNSCALE_TYPE_A         0x00000000
#define RCDF_VIDEO_DOWNSCALE_TYPE_B         0x00000040
#define RCDF_VIDEO_DOWNSCALE_TYPE_MASK      0x00000040

/* "RCDF_VIDEO_DOWNSCALER_COEFFICIENTS" BIT DEFINITIONS */

#define RCDF_VIDEO_DOWNSCALER_COEF1_POS     0
#define RCDF_VIDEO_DOWNSCALER_COEF2_POS     8
#define RCDF_VIDEO_DOWNSCALER_COEF3_POS     16
#define RCDF_VIDEO_DOWNSCALER_COEF4_POS     24
#define RCDF_VIDEO_DOWNSCALER_COEF_MASK     0xF

/* VIDEO DE-INTERLACING AND ALPHA CONTROL */

#define RCDF_NO_CK_OUTSIDE_ALPHA            0x00000100
#define RCDF_CSC_VIDEO_YUV_TO_RGB           0x00000400
#define RCDF_VIDEO_INPUT_IS_RGB             0x00002000
#define RCDF_ALPHA1_PRIORITY_POS			16
#define RCDF_ALPHA1_PRIORITY_MASK			0x00030000
#define RCDF_ALPHA2_PRIORITY_POS			18
#define RCDF_ALPHA2_PRIORITY_MASK			0x000C0000
#define RCDF_ALPHA3_PRIORITY_POS			20
#define RCDF_ALPHA3_PRIORITY_MASK			0x00300000

/* VIDEO CURSOR COLOR KEY DEFINITIONS */

#define RCDF_CURSOR_COLOR_KEY_ENABLE      0x20000000
#define RCDF_CURSOR_COLOR_KEY_OFFSET_POS  24
#define RCDF_CURSOR_COLOR_BITS            23
#define RCDF_COLOR_MASK                   0x00FFFFFF /* 24 significant bits */