gfx_regs.h

DirectFB-1.0.1可用于linux的嵌入式GUI

#define SC1200_TVOUT_YC_DELAY_NONE                0x00000000
#define SC1200_TVOUT_Y_DELAY_ONE_PIXEL            0x00400000
#define SC1200_TVOUT_C_DELAY_ONE_PIXEL            0x00800000
#define SC1200_TVOUT_C_DELAY_TWO_PIXELS           0x00C00000

/* TVOUT HORIZONTAL SCALING/CONTROL BIT DEFINITIONS */

#define SC1200_TVOUT_FLICKER_FILTER_MASK               0x60000000
#define SC1200_TVOUT_FLICKER_FILTER_FOURTH_HALF_FOURTH 0x00000000
#define SC1200_TVOUT_FLICKER_FILTER_HALF_ONE_HALF      0x20000000
#define SC1200_TVOUT_FLICKER_FILTER_DISABLED           0x40000000
#define SC1200_TVENC_EXTERNAL_RESET_INTERVAL_MASK      0x0F000000
#define SC1200_TVENC_EXTERNAL_RESET_EVERY_ODD_FIELD    0x00000000
#define SC1200_TVENC_EXTERNAL_RESET_EVERY_EVEN_FIELD   0x02000000
#define SC1200_TVENC_EXTERNAL_RESET_NEXT_ODD_FIELD     0x05000000
#define SC1200_TVENC_EXTERNAL_RESET_NEXT_EVEN_FIELD    0x07000000
#define SC1200_TVENC_EXTERNAL_RESET_EVERY_FIELD        0x0E000000
#define SC1200_TVENC_EXTERNAL_RESET_EVERY_X_ODD_FIELDS  0x08000000
#define SC1200_TVENC_EXTERNAL_RESET_EVERY_X_EVEN_FIELDS 0x0A000000

/* TVOUT DEBUG BIT DEFINITIONS */

#define SC1200_TVOUT_FIELD_STATUS_EVEN         0x00000040
#define SC1200_TVOUT_FIELD_STATUS_TV           0x00000080
#define SC1200_TVOUT_CRT_VSYNC_STATUS_TRAILING 0x00000100
#define SC1200_TVOUT_FIELD_STATUS_INVERT      0x00000200
#define SC1200_TVOUT_CONVERTER_INTERPOLATION   0x00000400

/* TVENC TIMING/CONTROL 1 BIT DEFINITIONS (REGISTER 0xC00) */

#define SC1200_TVENC_VPHASE_MASK                          0x001FF800
#define SC1200_TVENC_VPHASE_POS                           11
#define SC1200_TVENC_SUB_CARRIER_RESET_MASK               0x30000000
#define SC1200_TVENC_SUB_CARRIER_RESET_NEVER              0x00000000
#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_TWO_LINES    0x10000000
#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_TWO_FRAMES   0x20000000
#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_FOUR_FRAMES  0x30000000
#define SC1200_TVENC_VIDEO_TIMING_ENABLE                  0x80000000

/* TVENC TIMING/CONTROL 2 BIT DEFINITIONS (REGISTER 0xC04) */

#define SC1200_TVENC_OUTPUT_YCBCR                         0x40000000
#define SC1200_TVENC_CFS_MASK                             0x00030000
#define SC1200_TVENC_CFS_BYPASS                           0x00000000
#define SC1200_TVENC_CFS_CVBS                             0x00020000
#define SC1200_TVENC_CFS_SVIDEO                           0x00030000

/* TVENC TIMING/CONTROL 3 BIT DEFINITIONS (REGISTER 0xC08) */

#define SC1200_TVENC_CS                                   0x00000001
#define SC1200_TVENC_SYNCMODE_MASK                        0x00000006
#define SC1200_TVENC_SYNC_ON_GREEN                        0x00000002
#define SC1200_TVENC_SYNC_ON_CVBS                         0x00000004
#define SC1200_TVENC_CM                                   0x00000008

/* TVENC DAC CONTROL BIT DEFINITIONS (REGISTER 0xC2C) */
#define SC1200_TVENC_TRIM_MASK	               0x00000007
#define SC1200_TVENC_POWER_DOWN	               0x00000020

/* TVENC MV CONTROL BIT DEFINITIONS (REGISTER 0xC30) */
#define SC1200_TVENC_MV_ENABLE                 0xBE

/* SC1200 VIP REGISTER DEFINITIONS */

#define SC1200_VIP_CONFIG					0x00000000
#define SC1200_VIP_CONTROL					0x00000004
#define SC1200_VIP_STATUS					0x00000008
#define SC1200_VIP_CURRENT_LINE				0x00000010
#define SC1200_VIP_LINE_TARGET				0x00000014
#define SC1200_ODD_DIRECT_VBI_LINE_ENABLE   0x00000018
#define SC1200_EVEN_DIRECT_VBI_LINE_ENABLE  0x0000001C
#define SC1200_VIP_ODD_BASE					0x00000020
#define SC1200_VIP_EVEN_BASE				0x00000024
#define SC1200_VIP_PITCH					0x00000028
#define SC1200_VBI_ODD_BASE					0x00000040
#define SC1200_VBI_EVEN_BASE				0x00000044
#define SC1200_VBI_PITCH					0x00000048

/* "SC1200_VIP_CONFIG" BIT DEFINITIONS */

#define SC1200_VIP_MODE_MASK                0x00000003
#define	SC1200_VIP_MODE_C       			0x00000002
#define SC1200_VBI_ANCILLARY_TO_MEMORY      0x000C0000
#define SC1200_VBI_TASK_A_TO_MEMORY         0x00140000
#define SC1200_VBI_TASK_B_TO_MEMORY         0x00240000
#define SC1200_VIP_BUS_REQUEST_THRESHOLD    0x00400000

/* "SC1200_VIP_CONTROL" BIT DEFINITIONS */

#define SC1200_CAPTURE_RUN_MODE_MASK        0x00000003
#define SC1200_CAPTURE_RUN_MODE_STOP_LINE   0x00000000
#define SC1200_CAPTURE_RUN_MODE_STOP_FIELD  0x00000001
#define SC1200_CAPTURE_RUN_MODE_START       0x00000003
#define	SC1200_VIP_DATA_CAPTURE_EN			0x00000100
#define	SC1200_VIP_VBI_CAPTURE_EN			0x00000200
#define	SC1200_VIP_VBI_FIELD_INTERRUPT_EN	0x00010000

/* "SC1200_VIP_STATUS" BIT DEFINITIONS */

#define	SC1200_VIP_CURRENT_FIELD_ODD		0x01000000
#define SC1200_VIP_BASE_NOT_UPDATED         0x00200000
#define	SC1200_VIP_FIFO_OVERFLOW			0x00100000
#define	SC1200_VIP_CLEAR_LINE_INT			0x00020000
#define	SC1200_VIP_CLEAR_FIELD_INT			0x00010000
#define	SC1200_VBI_DATA_CAPTURE_ACTIVE		0x00000200
#define	SC1200_VIDEO_DATA_CAPTURE_ACTIVE	0x00000100

/* "SC1200_VIP_CURRENT_LINE" BIT DEFINITIONS */

#define SC1200_VIP_CURRENT_LINE_MASK	    0x000003FF

/* "SC1200_VIP_LINE_TARGET" BIT DEFINITIONS */

#define SC1200_VIP_LAST_LINE_MASK	        0x03FF0000

/* "SC1200_VIP_PITCH" BIT DEFINITION */

#define SC1200_VIP_PITCH_MASK               0x0000FFFC

/* "SC1200_VBI_PITCH" BIT DEFINITION */

#define SC1200_VBI_PITCH_MASK               0x0000FFFC

/* SC1200 DIRECT VBI LINE ENABLE BIT DEFINITION */

#define SC1200_DIRECT_VBI_LINE_ENABLE_MASK  0x00FFFFFF

/* SC1200 CONFIGURATION BLOCK */

#define SC1200_CB_BASE_ADDR                 0x9000
#define SC1200_CB_WDTO                      0x0000
#define SC1200_CB_WDCNFG                    0x0002
#define SC1200_CB_WDSTS                     0x0004
#define SC1200_CB_TMVALUE                   0x0008
#define SC1200_CB_TMCNFG                    0x000D
#define SC1200_CB_PMR                       0x0030
#define SC1200_CB_MCR                       0x0034
#define SC1200_CB_INTSEL                    0x0038
#define SC1200_CB_PID                       0x003C
#define SC1200_CB_REV                       0x003D

/* SC1200 HIGH RESOLUTION TIMER CONFIGURATION REGISTER BITS */

#define SC1200_TMCLKSEL_27MHZ               0x2

/*---------------------------------*/
/*  PHILIPS SAA7114 VIDEO DECODER  */
/*---------------------------------*/

#define SAA7114_CHIPADDR					0x42

/* VIDEO DECODER REGISTER DEFINITIONS */

#define SAA7114_ANALOG_INPUT_CTRL1			0x02
#define SAA7114_LUMINANCE_CONTROL           0x09
#define SAA7114_BRIGHTNESS					0x0A
#define SAA7114_CONTRAST					0x0B
#define SAA7114_SATURATION					0x0C
#define SAA7114_HUE							0x0D
#define SAA7114_STATUS						0x1F
#define SAA7114_IPORT_CONTROL				0x86

/* TASK A REGISTER DEFINITIONS */

#define SAA7114_TASK_A_HORZ_OUTPUT_LO		0x9C
#define SAA7114_TASK_A_HORZ_OUTPUT_HI		0x9D
#define SAA7114_TASK_A_HSCALE_LUMA_LO		0xA8
#define SAA7114_TASK_A_HSCALE_LUMA_HI		0xA9
#define SAA7114_TASK_A_HSCALE_CHROMA_LO		0xAC
#define SAA7114_TASK_A_HSCALE_CHROMA_HI		0xAD

/* TASK B REGISTER DEFINITIONS */

#define SAA7114_HORZ_OFFSET_LO				0xC4
#define SAA7114_HORZ_OFFSET_HI				0xC5
#define SAA7114_HORZ_INPUT_LO				0xC6
#define SAA7114_HORZ_INPUT_HI				0xC7
#define SAA7114_VERT_OFFSET_LO				0xC8
#define SAA7114_VERT_OFFSET_HI				0xC9
#define SAA7114_VERT_INPUT_LO				0xCA
#define SAA7114_VERT_INPUT_HI				0xCB
#define SAA7114_HORZ_OUTPUT_LO				0xCC
#define SAA7114_HORZ_OUTPUT_HI				0xCD
#define SAA7114_VERT_OUTPUT_LO				0xCE
#define SAA7114_VERT_OUTPUT_HI				0xCF
#define SAA7114_HORZ_PRESCALER				0xD0
#define SAA7114_HORZ_ACL					0xD1
#define SAA7114_HORZ_FIR_PREFILTER			0xD2
#define SAA7114_FILTER_CONTRAST				0xD5
#define SAA7114_FILTER_SATURATION			0xD6
#define SAA7114_HSCALE_LUMA_LO				0xD8
#define SAA7114_HSCALE_LUMA_HI				0xD9
#define SAA7114_HSCALE_CHROMA_LO			0xDC
#define SAA7114_HSCALE_CHROMA_HI			0xDD
#define SAA7114_VSCALE_LUMA_LO				0xE0
#define SAA7114_VSCALE_LUMA_HI				0xE1
#define SAA7114_VSCALE_CHROMA_LO			0xE2
#define SAA7114_VSCALE_CHROMA_HI			0xE3
#define SAA7114_VSCALE_CONTROL				0xE4
#define SAA7114_VSCALE_CHROMA_OFFS0			0xE8
#define SAA7114_VSCALE_CHROMA_OFFS1			0xE9
#define SAA7114_VSCALE_CHROMA_OFFS2			0xEA
#define SAA7114_VSCALE_CHROMA_OFFS3			0xEB
#define SAA7114_VSCALE_LUMINA_OFFS0			0xEC
#define SAA7114_VSCALE_LUMINA_OFFS1			0xED
#define SAA7114_VSCALE_LUMINA_OFFS2			0xEE
#define SAA7114_VSCALE_LUMINA_OFFS3			0xEF


/* Still need to determine PHO value (common phase offset) */
#define SAA7114_VSCALE_PHO					0x00


/*----------------------------------------------*/
/*  SECOND GENERATION GRAPHICS UNIT (REDCLOUD)  */
/*----------------------------------------------*/

#define MGP_DST_OFFSET			0x0000		/* dst address				*/
#define MGP_SRC_OFFSET			0x0004		/* src address				*/
#define MGP_VEC_ERR				0x0004		/* vector diag/axial errors	*/
#define MGP_STRIDE				0x0008		/* src and dst strides		*/
#define MGP_WID_HEIGHT			0x000C		/* width and height of BLT	*/
#define MGP_VEC_LEN				0x000C		/* vector length/init error */
#define MGP_SRC_COLOR_FG		0x0010		/* src mono data fgcolor 	*/
#define MGP_SRC_COLOR_BG		0x0014		/* src mono data bkcolor 	*/
#define MGP_PAT_COLOR_0			0x0018		/* pattern color 0			*/
#define MGP_PAT_COLOR_1			0x001C		/* pattern color 1			*/
#define MGP_PAT_COLOR_2			0x0020		/* pattern color 2			*/
#define MGP_PAT_COLOR_3			0x0024		/* pattern color 3			*/
#define MGP_PAT_COLOR_4			0x0028		/* pattern color 4			*/
#define MGP_PAT_COLOR_5			0x002C		/* pattern color 5			*/
#define MGP_PAT_DATA_0			0x0030		/* pattern data 0			*/
#define MGP_PAT_DATA_1			0x0034		/* pattern data 1			*/
#define MGP_RASTER_MODE			0x0038		/* raster operation			*/
#define MGP_VECTOR_MODE			0x003C		/* render vector			*/
#define MGP_BLT_MODE			0x0040		/* render BLT				*/
#define MGP_BLT_STATUS			0x0044		/* BLT status register		*/
#define MGP_RESET				0x0044		/* reset register (write)	*/
#define MGP_HST_SOURCE			0x0048		/* host src data (bitmap)	*/
#define MGP_BASE_OFFSET			0x004C		/* base render offset		*/

/* MGP_RASTER_MODE DEFINITIONS */

#define MGP_RM_BPPFMT_332		    0x00000000	/* 8 BPP, 3:3:2				*/
#define MGP_RM_BPPFMT_4444		    0x40000000	/* 16 BPP, 4:4:4:4			*/
#define MGP_RM_BPPFMT_1555		    0x50000000	/* 16 BPP, 1:5:5:5			*/
#define MGP_RM_BPPFMT_565		    0x60000000	/* 16 BPP, 5:6:5			*/
#define MGP_RM_BPPFMT_8888		    0x80000000	/* 32 BPP, 8:8:8:8			*/
#define MGP_RM_ALPHA_EN_MASK        0x00C00000  /* Alpha enable             */
#define MGP_RM_ALPHA_TO_RGB         0x00400000  /* Alpha applies to RGB     */
#define MGP_RM_ALPHA_TO_ALPHA       0x00800000  /* Alpha applies to alpha   */
#define MGP_RM_ALPHA_OP_MASK        0x00300000  /* Alpha operation          */
#define MGP_RM_ALPHA_TIMES_A        0x00000000  /* Alpha * A                */
#define MGP_RM_BETA_TIMES_B         0x00100000  /* (1-alpha) * B            */
#define MGP_RM_A_PLUS_BETA_B        0x00200000  /* A + (1-alpha) * B        */
#define MGP_RM_ALPHA_A_PLUS_BETA_B  0x00300000  /* alpha * A + (1 - alpha)B */
#define MGP_RM_ALPHA_SELECT         0x000E0000  /* Alpha Select             */
#define MGP_RM_SELECT_ALPHA_A       0x00000000  /* Alpha from channel A     */
#define MGP_RM_SELECT_ALPHA_B       0x00020000  /* Alpha from channel B     */
#define MGP_RM_SELECT_ALPHA_R       0x00040000  /* Registered alpha         */
#define MGP_RM_SELECT_ALPHA_1       0x00060000  /* Constant 1               */
#define MGP_RM_SELECT_ALPHA_CHAN_A  0x00080000  /* RGB Values from A        */
#define MGP_RM_SELECT_ALPHA_CHAN_B  0x000A0000  /* RGB Values from B        */
#define MGP_RM_DEST_FROM_CHAN_A     0x00010000  /* Alpha channel select     */
#define MGP_RM_PAT_FLAGS		    0x00000700  /* pattern related bits		*/
#define MGP_RM_PAT_MONO			    0x00000100  /* monochrome pattern		*/
#define MGP_RM_PAT_COLOR		    0x00000200  /* color pattern			*/
#define MGP_RM_PAT_TRANS		    0x00000400	/* pattern transparency		*/
#define MGP_RM_SRC_TRANS		    0x00000800	/* source transparency		*/

/* MGP_VECTOR_MODE DEFINITIONS */

#define MGP_VM_DST_REQ			0x00000008	/* dst data required		*/
#define MGP_VM_THROTTLE			0x00000010  /* sync to VBLANK			*/

/* MGP_BLT_MODE DEFINITIONS */

#define MGP_BM_SRC_FB			0x00000001  /* src = frame buffer		*/
#define MGP_BM_SRC_HOST			0x00000002  /* src = host register		*/
#define MGP_BM_DST_REQ			0x00000004  /* dst data required		*/
#define MGP_BM_SRC_MONO			0x00000040  /* monochrome source data   */
#define MGP_BM_SRC_BP_MONO      0x00000080  /* Byte-packed monochrome   */
#define MGP_BM_NEG_YDIR			0x00000100  /* negative Y direction		*/
#define MGP_BM_NEG_XDIR			0x00000200  /* negative X direction		*/
#define MGP_BM_THROTTLE			0x00000400  /* sync to VBLANK			*/

/* MGP_BLT_STATUS DEFINITIONS */

#define MGP_BS_BLT_BUSY			0x00000001  /* GP is not idle			*/
#define MGP_BS_BLT_PENDING		0x00000004	/* second BLT is pending	*/
#define MGP_BS_HALF_EMPTY		0x00000008  /* src FIFO half empty		*/

/* ALPHA BLENDING MODES       */

#define ALPHA_MODE_BLEND        0x00000000

/*---------------------------------------------------*/
/*  SECOND GENERATION DISPLAY CONTROLLER (REDCLOUD)  */
/*---------------------------------------------------*/

#define MDC_UNLOCK              0x00000000  /* Unlock register               */
#define MDC_GENERAL_CFG         0x00000004  /* Config registers              */
#define MDC_DISPLAY_CFG         0x00000008  
#define MDC_GFX_SCL             0x0000000C  /* Graphics scaling              */

#define MDC_FB_ST_OFFSET        0x00000010  /* Frame buffer start offset     */
#define MDC_CB_ST_OFFSET        0x00000014  /* Compression start offset      */
#define MDC_CURS_ST_OFFSET      0x00000018  /* Cursor buffer start offset    */
#define MDC_ICON_ST_OFFSET      0x0000001C  /* Icon buffer start offset      */
#define MDC_VID_Y_ST_OFFSET     0x00000020  /* Video Y Buffer start offset   */
#define MDC_VID_U_ST_OFFSET     0x00000024  /* Video U Buffer start offset   */
#define MDC_VID_V_ST_OFFSET     0x00000028  /* Video V Buffer start offset   */
#define MDC_LINE_SIZE           0x00000030  /* Video, CB, and FB line sizes  */
#define MDC_GFX_PITCH           0x00000034  /* FB and DB skip counts         */
#define MDC_VID_YUV_PITCH       0x00000038  /* Y, U and V buffer skip counts */

#define MDC_H_ACTIVE_TIMING     0x00000040  /* Horizontal timings            */
#define MDC_H_BLANK_TIMING      0x00000044
#define MDC_H_SYNC_TIMING       0x00000048
#define MDC_V_ACTIVE_TIMING     0x00000050  /* Vertical Timings              */