gfx_regs.h

DirectFB-1.0.1可用于linux的嵌入式GUI

#define DC_TCFG_DDCK		0x00000010		/* DDC clock                */
#define DC_TCFG_TGEN		0x00000020		/* timing generator enable  */
#define DC_TCFG_VIEN		0x00000040		/* vertical interrupt enable*/
#define DC_TCFG_BLNK		0x00000080		/* blink enable             */
#define DC_TCFG_CHSP		0x00000100		/* horizontal sync polarity */
#define DC_TCFG_CVSP		0x00000200		/* vertical sync polarity   */
#define DC_TCFG_FHSP		0x00000400		/* panel horz sync polarity */
#define DC_TCFG_FVSP		0x00000800		/* panel vert sync polarity */
#define DC_TCFG_FCEN		0x00001000		/* flat-panel centering     */
#define DC_TCFG_CDCE		0x00002000		/* HACK - 1.3 definition	*/
#define DC_TCFG_PLNR		0x00002000		/* planar mode enable		*/
#define DC_TCFG_INTL		0x00004000		/* interlace scan           */
#define DC_TCFG_PXDB		0x00008000		/* pixel double             */
#define DC_TCFG_BKRT		0x00010000		/* blink rate               */
#define DC_TCFG_PSD_MASK	0x000E0000		/* power sequence delay     */
#define DC_TCFG_PSD_POS		17				/* power sequence delay     */
#define DC_TCFG_DDCI		0x08000000		/* DDC input (RO)           */
#define DC_TCFG_SENS		0x10000000		/* monitor sense (RO)       */
#define DC_TCFG_DNA			0x20000000		/* display not active (RO)  */
#define DC_TCFG_VNA			0x40000000		/* vertical not active (RO) */
#define DC_TCFG_VINT		0x80000000		/* vertical interrupt (RO)  */

/* "DC_OUTPUT_CFG" BIT DEFINITIONS */

#define DC_OCFG_8BPP		0x00000001		/* 8/16 bpp select          */
#define DC_OCFG_555			0x00000002		/* 16 bpp format            */
#define DC_OCFG_PCKE		0x00000004		/* PCLK enable              */
#define DC_OCFG_FRME		0x00000008		/* frame rate mod enable    */
#define DC_OCFG_DITE		0x00000010		/* dither enable            */
#define DC_OCFG_2PXE		0x00000020		/* 2 pixel enable           */
#define DC_OCFG_2XCK		0x00000040		/* 2 x pixel clock          */
#define DC_OCFG_2IND		0x00000080		/* 2 index enable           */
#define DC_OCFG_34ADD		0x00000100		/* 3- or 4-bit add          */
#define DC_OCFG_FRMS		0x00000200		/* frame rate mod select    */
#define DC_OCFG_CKSL		0x00000400		/* clock select             */
#define DC_OCFG_PRMP		0x00000800		/* palette re-map           */
#define DC_OCFG_PDEL		0x00001000		/* panel data enable low    */
#define DC_OCFG_PDEH		0x00002000		/* panel data enable high   */
#define DC_OCFG_CFRW		0x00004000		/* comp line buffer r/w sel */
#define DC_OCFG_DIAG		0x00008000		/* comp line buffer diag    */

#define MC_MEM_CNTRL1       0x00008400
#define MC_DR_ADD			0x00008418
#define MC_DR_ACC			0x0000841C

/* MC_MEM_CNTRL1 BIT DEFINITIONS */

#define MC_XBUSARB          0x00000008      /* 0 = GP priority < CPU priority */
											/* 1 = GP priority = CPU priority */
											/* GXm databook V2.0 is wrong ! */
/*----------*/
/*  CS5530  */
/*----------*/

/* CS5530 REGISTER DEFINITIONS */

#define CS5530_VIDEO_CONFIG 		0x0000
#define CS5530_DISPLAY_CONFIG       0x0004
#define CS5530_VIDEO_X_POS          0x0008
#define CS5530_VIDEO_Y_POS          0x000C
#define CS5530_VIDEO_SCALE          0x0010
#define CS5530_VIDEO_COLOR_KEY		0x0014
#define CS5530_VIDEO_COLOR_MASK		0x0018
#define CS5530_PALETTE_ADDRESS 		0x001C
#define CS5530_PALETTE_DATA	 		0x0020
#define CS5530_DOT_CLK_CONFIG       0x0024
#define CS5530_CRCSIG_TFT_TV        0x0028

/* "CS5530_VIDEO_CONFIG" BIT DEFINITIONS */

#define CS5530_VCFG_VID_EN					0x00000001	
#define CS5530_VCFG_VID_REG_UPDATE			0x00000002	
#define CS5530_VCFG_VID_INP_FORMAT			0x0000000C	
#define CS5530_VCFG_8_BIT_4_2_0				0x00000004
#define CS5530_VCFG_16_BIT_4_2_0			0x00000008
#define CS5530_VCFG_GV_SEL					0x00000010	
#define CS5530_VCFG_CSC_BYPASS				0x00000020	
#define CS5530_VCFG_X_FILTER_EN				0x00000040	
#define CS5530_VCFG_Y_FILTER_EN				0x00000080	
#define CS5530_VCFG_LINE_SIZE_LOWER_MASK	0x0000FF00	
#define CS5530_VCFG_INIT_READ_MASK			0x01FF0000	
#define CS5530_VCFG_EARLY_VID_RDY  			0x02000000	
#define CS5530_VCFG_LINE_SIZE_UPPER			0x08000000	
#define CS5530_VCFG_4_2_0_MODE				0x10000000	
#define CS5530_VCFG_16_BIT_EN				0x20000000
#define CS5530_VCFG_HIGH_SPD_INT			0x40000000

/* "CS5530_DISPLAY_CONFIG" BIT DEFINITIONS */

#define CS5530_DCFG_DIS_EN					0x00000001	
#define CS5530_DCFG_HSYNC_EN				0x00000002	
#define CS5530_DCFG_VSYNC_EN				0x00000004	
#define CS5530_DCFG_DAC_BL_EN				0x00000008	
#define CS5530_DCFG_DAC_PWDNX				0x00000020	
#define CS5530_DCFG_FP_PWR_EN				0x00000040	
#define CS5530_DCFG_FP_DATA_EN				0x00000080	
#define CS5530_DCFG_CRT_HSYNC_POL 			0x00000100	
#define CS5530_DCFG_CRT_VSYNC_POL 			0x00000200	
#define CS5530_DCFG_FP_HSYNC_POL  			0x00000400	
#define CS5530_DCFG_FP_VSYNC_POL  			0x00000800	
#define CS5530_DCFG_XGA_FP		  			0x00001000	
#define CS5530_DCFG_FP_DITH_EN				0x00002000	
#define CS5530_DCFG_CRT_SYNC_SKW_MASK		0x0001C000
#define CS5530_DCFG_CRT_SYNC_SKW_INIT		0x00010000
#define CS5530_DCFG_PWR_SEQ_DLY_MASK		0x000E0000
#define CS5530_DCFG_PWR_SEQ_DLY_INIT		0x00080000
#define CS5530_DCFG_VG_CK					0x00100000
#define CS5530_DCFG_GV_PAL_BYP				0x00200000
#define CS5530_DCFG_DDC_SCL					0x00400000
#define CS5530_DCFG_DDC_SDA					0x00800000
#define CS5530_DCFG_DDC_OE					0x01000000
#define CS5530_DCFG_16_BIT_EN				0x02000000


/*----------*/
/*  SC1200  */
/*----------*/

/* SC1200 VIDEO REGISTER DEFINITIONS */

#define SC1200_VIDEO_CONFIG 				0x000
#define SC1200_DISPLAY_CONFIG				0x004
#define SC1200_VIDEO_X_POS					0x008
#define SC1200_VIDEO_Y_POS					0x00C
#define SC1200_VIDEO_UPSCALE				0x010
#define SC1200_VIDEO_COLOR_KEY				0x014
#define SC1200_VIDEO_COLOR_MASK				0x018
#define SC1200_PALETTE_ADDRESS 				0x01C
#define SC1200_PALETTE_DATA	 				0x020
#define SC1200_VID_MISC						0x028
#define SC1200_VID_CLOCK_SELECT				0x02C
#define SC1200_VIDEO_DOWNSCALER_CONTROL     0x03C 
#define SC1200_VIDEO_DOWNSCALER_COEFFICIENTS 0x40  
#define SC1200_VID_CRC						0x044
#define SC1200_DEVICE_ID					0x048
#define SC1200_VID_ALPHA_CONTROL			0x04C
#define SC1200_CURSOR_COLOR_KEY				0x050
#define SC1200_CURSOR_COLOR_MASK			0x054
#define SC1200_CURSOR_COLOR_1				0x058
#define SC1200_CURSOR_COLOR_2				0x05C
#define SC1200_ALPHA_XPOS_1					0x060
#define SC1200_ALPHA_YPOS_1					0x064
#define SC1200_ALPHA_COLOR_1				0x068
#define SC1200_ALPHA_CONTROL_1				0x06C
#define SC1200_ALPHA_XPOS_2					0x070
#define SC1200_ALPHA_YPOS_2					0x074
#define SC1200_ALPHA_COLOR_2				0x078
#define SC1200_ALPHA_CONTROL_2				0x07C
#define SC1200_ALPHA_XPOS_3					0x080
#define SC1200_ALPHA_YPOS_3					0x084
#define SC1200_ALPHA_COLOR_3				0x088
#define SC1200_ALPHA_CONTROL_3				0x08C
#define SC1200_VIDEO_REQUEST                0x090
#define SC1200_ALPHA_WATCH 					0x094
#define SC1200_VIDEO_DISPLAY_MODE           0x400
#define SC1200_VIDEO_ODD_VBI_LINE_ENABLE    0x40C
#define SC1200_VIDEO_EVEN_VBI_LINE_ENABLE   0x410
#define SC1200_VIDEO_VBI_HORIZ_CONTROL      0x414
#define SC1200_VIDEO_ODD_VBI_TOTAL_COUNT    0x418
#define SC1200_VIDEO_EVEN_VBI_TOTAL_COUNT   0x41C
#define SC1200_GENLOCK                      0x420
#define SC1200_GENLOCK_DELAY                0x424
#define SC1200_TVOUT_HORZ_TIM				0x800
#define SC1200_TVOUT_HORZ_SYNC				0x804
#define SC1200_TVOUT_VERT_SYNC				0x808
#define SC1200_TVOUT_LINE_END				0x80C
#define SC1200_TVOUT_VERT_DOWNSCALE			0x810 /* REV. A & B */
#define SC1200_TVOUT_HORZ_PRE_ENCODER_SCALE 0x810 /* REV. C */
#define SC1200_TVOUT_HORZ_SCALING			0x814
#define SC1200_TVOUT_DEBUG                  0x818
#define SC1200_TVENC_TIM_CTRL_1				0xC00
#define SC1200_TVENC_TIM_CTRL_2				0xC04
#define SC1200_TVENC_TIM_CTRL_3				0xC08
#define SC1200_TVENC_SUB_FREQ				0xC0C
#define SC1200_TVENC_DISP_POS				0xC10
#define SC1200_TVENC_DISP_SIZE				0xC14
#define SC1200_TVENC_CC_DATA				0xC18
#define SC1200_TVENC_EDS_DATA				0xC1C
#define SC1200_TVENC_CGMS_DATA				0xC20
#define SC1200_TVENC_WSS_DATA				0xC24
#define SC1200_TVENC_CC_CONTROL				0xC28
#define SC1200_TVENC_DAC_CONTROL			0xC2C
#define SC1200_TVENC_MV_CONTROL             0xC30

/* "SC1200_VIDEO_CONFIG" BIT DEFINITIONS */

#define SC1200_VCFG_VID_EN					0x00000001	
#define SC1200_VCFG_VID_INP_FORMAT			0x0000000C	
#define SC1200_VCFG_UYVY_FORMAT				0x00000000
#define SC1200_VCFG_Y2YU_FORMAT				0x00000004
#define SC1200_VCFG_YUYV_FORMAT				0x00000008
#define SC1200_VCFG_YVYU_FORMAT				0x0000000C
#define SC1200_VCFG_X_FILTER_EN				0x00000040	
#define SC1200_VCFG_Y_FILTER_EN				0x00000080	
#define SC1200_VCFG_LINE_SIZE_LOWER_MASK	0x0000FF00	
#define SC1200_VCFG_INIT_READ_MASK			0x01FF0000	
#define SC1200_VCFG_LINE_SIZE_UPPER			0x08000000	
#define SC1200_VCFG_4_2_0_MODE				0x10000000	

/* "SC1200_DISPLAY_CONFIG" BIT DEFINITIONS */

#define SC1200_DCFG_DIS_EN					0x00000001	
#define SC1200_DCFG_HSYNC_EN				0x00000002	
#define SC1200_DCFG_VSYNC_EN				0x00000004	
#define SC1200_DCFG_DAC_BL_EN				0x00000008	
#define SC1200_DCFG_FP_PWR_EN				0x00000040
#define SC1200_DCFG_FP_DATA_EN				0x00000080	
#define SC1200_DCFG_CRT_HSYNC_POL 			0x00000100	
#define SC1200_DCFG_CRT_VSYNC_POL 			0x00000200	
#define SC1200_DCFG_CRT_SYNC_SKW_MASK		0x0001C000
#define SC1200_DCFG_CRT_SYNC_SKW_INIT		0x00010000
#define SC1200_DCFG_PWR_SEQ_DLY_MASK		0x000E0000
#define SC1200_DCFG_PWR_SEQ_DLY_INIT		0x00080000
#define SC1200_DCFG_VG_CK					0x00100000
#define SC1200_DCFG_GV_PAL_BYP				0x00200000
#define SC1200_DCFG_DDC_SCL					0x00400000
#define SC1200_DCFG_DDC_SDA					0x00800000
#define SC1200_DCFG_DDC_OE					0x01000000

/* "SC1200_VID_MISC" BIT DEFINITIONS */

#define SC1200_GAMMA_BYPASS_BOTH            0x00000001
#define SC1200_DAC_POWER_DOWN               0x00000400
#define SC1200_ANALOG_POWER_DOWN            0x00000800
#define SC1200_PLL_POWER_NORMAL             0x00001000

/* "SC1200_VIDEO_DOWNSCALER_CONTROL" BIT DEFINITIONS */

#define SC1200_VIDEO_DOWNSCALE_ENABLE       0x00000001
#define SC1200_VIDEO_DOWNSCALE_FACTOR_POS   1
#define SC1200_VIDEO_DOWNSCALE_FACTOR_MASK  0x0000001E
#define SC1200_VIDEO_DOWNSCALE_TYPE_A       0x00000000
#define SC1200_VIDEO_DOWNSCALE_TYPE_B       0x00000040
#define SC1200_VIDEO_DOWNSCALE_TYPE_MASK    0x00000040

/* "SC1200_VIDEO_DOWNSCALER_COEFFICIENTS" BIT DEFINITIONS */

#define SC1200_VIDEO_DOWNSCALER_COEF1_POS   0
#define SC1200_VIDEO_DOWNSCALER_COEF2_POS   8
#define SC1200_VIDEO_DOWNSCALER_COEF3_POS   16
#define SC1200_VIDEO_DOWNSCALER_COEF4_POS   24
#define SC1200_VIDEO_DOWNSCALER_COEF_MASK   0xF

/* VIDEO DE-INTERLACING AND ALPHA CONTROL (REGISTER 0x4C) */

#define SC1200_VERTICAL_SCALER_SHIFT_MASK   0x00000007
#define SC1200_VERTICAL_SCALER_SHIFT_INIT   0x00000004
#define SC1200_VERTICAL_SCALER_SHIFT_EN     0x00000010
#define SC1200_TOP_LINE_IN_ODD              0x00000040
#define SC1200_NO_CK_OUTSIDE_ALPHA          0x00000100
#define SC1200_VIDEO_IS_INTERLACED          0x00000200
#define SC1200_CSC_VIDEO_YUV_TO_RGB         0x00000400
#define SC1200_CSC_GFX_RGB_TO_YUV           0x00000800
#define SC1200_VIDEO_INPUT_IS_RGB           0x00002000
#define SC1200_VIDEO_LINE_OFFSET_ODD        0x00001000
#define SC1200_ALPHA1_PRIORITY_POS			16
#define SC1200_ALPHA1_PRIORITY_MASK			0x00030000
#define SC1200_ALPHA2_PRIORITY_POS			18
#define SC1200_ALPHA2_PRIORITY_MASK			0x000C0000
#define SC1200_ALPHA3_PRIORITY_POS			20
#define SC1200_ALPHA3_PRIORITY_MASK			0x00300000

/* VIDEO CURSOR COLOR KEY DEFINITIONS (REGISTER 0x50) */

#define SC1200_CURSOR_COLOR_KEY_OFFSET_POS  24
#define SC1200_CURSOR_COLOR_BITS            23
#define SC1200_COLOR_MASK                   0x00FFFFFF /* 24 significant bits */

/* ALPHA COLOR BIT DEFINITION (REGISTERS 0x68, 0x78, AND 0x88) */

#define SC1200_ALPHA_COLOR_ENABLE           0x01000000

/* ALPHA CONTROL BIT DEFINITIONS (REGISTERS 0x6C, 0x7C, AND 0x8C) */

#define SC1200_ACTRL_WIN_ENABLE				0x00010000
#define SC1200_ACTRL_LOAD_ALPHA				0x00020000

/* VIDEO REQUEST DEFINITIONS (REGISTER 0x90) */

#define SC1200_VIDEO_Y_REQUEST_POS          0
#define SC1200_VIDEO_X_REQUEST_POS          16
#define SC1200_VIDEO_REQUEST_MASK           0x00000FFF

/* VIDEO DISPLAY MODE (REGISTER 0x400) */

#define SC1200_VIDEO_SOURCE_MASK            0x00000003
#define SC1200_VIDEO_SOURCE_GX1             0x00000000
#define SC1200_VIDEO_SOURCE_DVIP            0x00000002
#define SC1200_VBI_SOURCE_MASK              0x00000004
#define SC1200_VBI_SOURCE_DVIP              0x00000000
#define SC1200_VBI_SOURCE_GX1               0x00000004

/* ODD/EVEN VBI LINE ENABLE (REGISTERS 0x40C, 0x410) */

#define SC1200_VIDEO_VBI_LINE_ENABLE_MASK   0x00FFFFFC
#define SC1200_VIDEO_ALL_ACTIVE_IS_VBI      0x01000000
#define SC1200_VIDEO_VBI_LINE_OFFSET_POS    25
#define SC1200_VIDEO_VBI_LINE_OFFSET_MASK   0x3E000000

/* ODD/EVEN VBI TOTAL COUNT (REGISTERS 0x418, 0x41C) */

#define SC1200_VIDEO_VBI_TOTAL_COUNT_MASK   0x000FFFFF

/* GENLOCK BIT DEFINITIONS */

#define SC1200_GENLOCK_SINGLE_ENABLE              0x00000001
#define SC1200_GENLOCK_FIELD_SYNC_ENABLE          0x00000001
#define SC1200_GENLOCK_CONTINUOUS_ENABLE          0x00000002
#define SC1200_GENLOCK_GX_VSYNC_FALLING_EDGE      0x00000004
#define SC1200_GENLOCK_VIP_VSYNC_FALLING_EDGE     0x00000008
#define SC1200_GENLOCK_TIMEOUT_ENABLE             0x00000010
#define SC1200_GENLOCK_TVENC_RESET_EVEN_FIELD     0x00000020
#define SC1200_GENLOCK_TVENC_RESET_BEFORE_DELAY   0x00000040
#define SC1200_GENLOCK_TVENC_RESET_ENABLE         0x00000080
#define SC1200_GENLOCK_SYNC_TO_TVENC              0x00000100
#define SC1200_GENLOCK_DELAY_MASK                 0x001FFFFF

/* TVOUT HORIZONTAL PRE ENCODER SCALE BIT DEFINITIONS */

#define SC1200_TVOUT_YC_DELAY_MASK                0x00C00000