small.bdf

硬件描述语言VHDL的最小内核nios设计,满足了内核的基本需要。

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/
(header "graphic" (version "1.3"))
(pin
	(input)
	(rect -16 456 152 472)
	(text "INPUT" (rect 133 0 161 11)(font "Arial" (font_size 6)))
	(text "PLD_CLOCKINPUT[1]" (rect 9 0 108 11)(font "Arial" ))
	(pt 168 8)
	(drawing
		(line (pt 92 12)(pt 117 12)(line_width 1))
		(line (pt 92 4)(pt 117 4)(line_width 1))
		(line (pt 121 8)(pt 168 8)(line_width 1))
		(line (pt 92 12)(pt 92 4)(line_width 1))
		(line (pt 117 4)(pt 121 8)(line_width 1))
		(line (pt 117 12)(pt 121 8)(line_width 1))
	)
	(text "VCC" (rect 136 7 157 18)(font "Arial" (font_size 6)))
	(annotation_block (location)(rect -136 464 -40 488))
)
(pin
	(input)
	(rect -16 440 152 456)
	(text "INPUT" (rect 133 0 161 11)(font "Arial" (font_size 6)))
	(text "PLD_CLEAR_N" (rect 9 0 82 11)(font "Arial" ))
	(pt 168 8)
	(drawing
		(line (pt 92 12)(pt 117 12)(line_width 1))
		(line (pt 92 4)(pt 117 4)(line_width 1))
		(line (pt 121 8)(pt 168 8)(line_width 1))
		(line (pt 92 12)(pt 92 4)(line_width 1))
		(line (pt 117 4)(pt 121 8)(line_width 1))
		(line (pt 117 12)(pt 121 8)(line_width 1))
	)
	(text "VCC" (rect 136 7 157 18)(font "Arial" (font_size 6)))
	(annotation_block (location)(rect -136 400 -48 424))
)
(pin
	(output)
	(rect 456 488 632 504)
	(text "OUTPUT" (rect 1 0 38 11)(font "Arial" (font_size 6)))
	(text "out_port_from_the_led_pio[7..0]" (rect 90 0 235 11)(font "Arial" ))
	(pt 0 8)
	(drawing
		(line (pt 0 8)(pt 52 8)(line_width 1))
		(line (pt 52 4)(pt 78 4)(line_width 1))
		(line (pt 52 12)(pt 78 12)(line_width 1))
		(line (pt 52 12)(pt 52 4)(line_width 1))
		(line (pt 78 4)(pt 82 8)(line_width 1))
		(line (pt 82 8)(pt 78 12)(line_width 1))
		(line (pt 78 12)(pt 82 8)(line_width 1))
	)
	(annotation_block (location)(rect 664 496 744 600))
)
(symbol
	(rect 176 416 432 528)
	(text "small_1c20" (rect 4 0 53 11)(font "Arial" (font_size 10)))
	(text "inst" (rect 4 96 20 107)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "reset_n " (rect 0 0 35 11)(font "Arial" (font_size 8)))
		(text "reset_n " (rect 20 25 55 36)(font "Arial" (font_size 8)))
		(line (pt 0 32)(pt 16 32)(line_width 1))
	)
	(port
		(pt 0 48)
		(input)
		(text "sys_clk " (rect 0 0 34 11)(font "Arial" (font_size 8)))
		(text "sys_clk " (rect 20 41 54 52)(font "Arial" (font_size 8)))
		(line (pt 0 48)(pt 16 48)(line_width 1))
	)
	(port
		(pt 256 80)
		(output)
		(text "out_port_from_the_led_pio[7..0] " (rect 0 0 147 11)(font "Arial" (font_size 8)))
		(text "out_port_from_the_led_pio[7..0] " (rect 76 73 223 84)(font "Arial" (font_size 8)))
		(line (pt 240 80)(pt 256 80)(line_width 3))
	)
	(drawing
		(line (pt 16 64)(pt 239 64)(color 0 0 0)(dotted)(line_width 1))
		(rectangle (rect 16 16 240 96)(line_width 1))
	)
)
(connector
	(pt 432 496)
	(pt 456 496)
	(bus)
)
(connector
	(pt 152 448)
	(pt 176 448)
)
(connector
	(pt 152 464)
	(pt 176 464)
)
(text "small -- Nios II, Cyclone 1C20" (rect 40 104 342 127)(font "Arial" (color 0 0 0)(font_size 18)))
(text "system does not contain a JTAG debug module,. meaning you cannot debug" (rect 40 192 365 203)(font "Arial" (color 0 0 0)(font_size 8)))
(text "system, you must perform the following steps:" (rect 40 224 237 235)(font "Arial" (color 0 0 0)(font_size 8)))
(text "the system or download software using Nios II IDE.  To run software on this" (rect 40 208 365 219)(font "Arial" (color 0 0 0)(font_size 8)))
(text "3.)  Recompile the hardware design.  This integrates the newly created memory" (rect 48 296 384 307)(font "Arial" (color 0 0 0)(font_size 8)))
(text "4.)  Download the design's SOF file to the FPGA using the Quartus Programmer." (rect 48 328 396 339)(font "Arial" (color 0 0 0)(font_size 8)))
(text "1.)  Build the software project in Nios II IDE.  This will create a memory initialization" (rect 48 248 403 259)(font "Arial" (color 0 0 0)(font_size 8)))
(text "file named \"onchip_ram.hex\" in this project's directory." (rect 64 264 301 275)(font "Arial" (color 0 0 0)(font_size 8)))
(text "2.)  In Quartus, re-open this project if it has been closed." (rect 48 280 289 291)(font "Arial" (color 0 0 0)(font_size 8)))
(text "initialization file (program memory) into the design's onchip memory." (rect 64 312 360 323)(font "Arial" (color 0 0 0)(font_size 8)))
(text "Warning:  To make this example as small as possible, the Nios II module in the" (rect 40 176 369 187)(font "Arial" (color 0 0 0)(font_size 8)))
(text "This design demonstrates the smallest possible functioning Nios II system." (rect 40 136 359 147)(font "Arial" (color 0 0 0)(font_size 8)))
(text "5.)  The system will boot out of onchip_ram and run." (rect 48 344 272 355)(font "Arial" (color 0 0 0)(font_size 8)))