hd_reg.s

s3c2440的LCD控制器驱动程序 ps 无操作系统的情况

TEMP_STACK_TOP  EQU    0x33DFFFFC



WTCON           EQU    0x53000000

    
USR26_MODE      EQU    0x00
FIQ26_MODE      EQU    0x01
IRQ26_MODE      EQU    0x02
SVC26_MODE      EQU    0x03
USR_MODE        EQU    0x10
FIQ_MODE        EQU    0x11
IRQ_MODE        EQU    0x12
SVC_MODE        EQU    0x13
ABT_MODE        EQU    0x17
UND_MODE        EQU    0x1b
SYSTEM_MODE     EQU    0x1f
MODE_MASK       EQU    0x1f
F_BIT           EQU    0x40
I_BIT           EQU    0x80
CC_V_BIT        EQU    0x10000000
CC_C_BIT        EQU    0x20000000
CC_Z_BIT        EQU    0x40000000
CC_N_BIT        EQU    0x80000000



;GPIO 
GPIO_CTL_BASE   EQU    0x56000000
; Offset 
oGPIO_CON       EQU    0x0  
oGPIO_DAT       EQU    0x4  
oGPIO_UP        EQU    0x8
oGPIO_RESERVED  EQU    0xC
oGPIO_A         EQU    0x00
oGPIO_B         EQU    0x10
oGPIO_C         EQU    0x20
oGPIO_D         EQU    0x30
oGPIO_E         EQU    0x40
oGPIO_F         EQU    0x50
oGPIO_G         EQU    0x60
oGPIO_H         EQU    0x70
oMISCCR         EQU    0x80 
oDCLKCON        EQU    0x84 
oEXTINT0        EQU    0x88  
oEXTINT1        EQU    0x8C  
oEXTINT2        EQU    0x90  
oEINTFLT0       EQU    0x94  
oEINTFLT1       EQU    0x98  
oEINTFLT2       EQU    0x9C  
oEINTFLT3       EQU    0xA0  
oEINTMASK       EQU    0xA4 
oEINTPEND       EQU    0xA8

; inital values for GPIOs 
vGPACON         EQU    0x007fffff
vGPBCON         EQU    0x00044555
vGPBUP          EQU    0x000007ff
vGPCCON         EQU    0xaaaaaaaa
vGPCUP          EQU    0x0000ffff
vGPDCON         EQU    0xaaaaaaaa
vGPDUP          EQU    0x0000ffff
vGPECON         EQU    0xaaaaaaaa
vGPEUP          EQU    0x0000ffff
vGPFCON         EQU    0x000055aa
vGPFUP          EQU    0x000000ff
vGPGCON         EQU    0xff95ffba
vGPGUP          EQU    0x0000ffff
vGPHCON         EQU    0x0016faaa
vGPHUP          EQU    0x000007ff
vEXTINT0        EQU    0x22222222
vEXTINT1        EQU    0x22222222
vEXTINT2        EQU    0x22222222



; Interrupts 
INT_CTL_BASE        EQU    0x4A000000
; Offset 
oSRCPND             EQU    0x00
oINTMOD             EQU    0x04
oINTMSK             EQU    0x08
oPRIORITY           EQU    0x0a
oINTPND             EQU    0x10
oINTOFFSET          EQU    0x14
oSUBSRCPND          EQU    0x18
oINTSUBMSK          EQU    0x1C

INT_RTC             EQU    0x40000000





; Clock and Power Management  
CLK_CTL_BASE        EQU    0x4C000000
; Offset  
oLOCKTIME           EQU    0x00  ; R/W, PLL lock time count register  
oMPLLCON            EQU    0x04  ; R/W, MPLL configuration register  
oUPLLCON            EQU    0x08  ; R/W, UPLL configuration register  
oCLKCON             EQU    0x0C  ; R/W, Clock generator control reg.  
oCLKSLOW            EQU    0x10  ; R/W, Slow clock control register  
oCLKDIVN            EQU    0x14  ; R/W, Clock divider control  






; initial values for DRAM
MEM_CTL_BASE    EQU    0x48000000  

vBWSCON         EQU    0x22111110
vBANKCON0       EQU    0x00000700
vBANKCON1       EQU    0x00000700
vBANKCON2       EQU    0x00000700
vBANKCON3       EQU    0x00000700
vBANKCON4       EQU    0x00000700
vBANKCON5       EQU    0x00000700
vBANKCON6       EQU    0x00018009
vBANKCON7       EQU    0x00018009
vREFRESH        EQU    0x008e04eb
vBANKSIZE       EQU    0xB2
vMRSRB6         EQU    0x30
vMRSRB7         EQU    0x30

vLOCKTIME       EQU    0x00ffffff          ; It's a default value  
vCLKCON         EQU    0x0000fff8          ; It's a default value  




; UART  
UART_CTL_BASE   EQU    0x50000000
UART0_CTL_BASE  EQU    0x50000000
UART1_CTL_BASE  EQU    0x50004000
UART2_CTL_BASE  EQU    0x50008000
UART_PCLK       EQU    50000000
UART_BAUD_RATE  EQU    115200
UART_BRD        EQU    26                   ;UART_BRD = ((UART_PCLK  / (UART_BAUD_RATE * 16)) - 1)
FIN             EQU    12000000
UTRSTAT_TX_EMPTY   EQU    0x4  
UTRSTAT_RX_READY   EQU    0x1
UART_ERR_MASK      EQU    0xF 
; Offset  
oULCON          EQU    0x00    ; R/W, UART line control register  
oUCON           EQU    0x04    ; R/W, UART control register  
oUFCON          EQU    0x08    ; R/W, UART FIFO control register  
oUMCON          EQU    0x0C    ; R/W, UART modem control register  
oUTRSTAT        EQU    0x10    ; R  , UART Tx/Rx status register  
oUERSTAT        EQU    0x14    ; R  , UART Rx error status register  
oUFSTAT         EQU    0x18    ; R  , UART FIFO status register  
oUMSTAT         EQU    0x1C    ; R  , UART Modem status register  
oUTXHL          EQU    0x20    ; W, UART transmit(little-end) buffer  
oUTXHB          EQU    0x23    ; W, UART transmit(big-end) buffer  
oURXHL          EQU    0x24    ; R  , UART receive(little-end) buffer  
oURXHB          EQU    0x27    ; R  , UART receive(big-end) buffer  
oUBRDIV         EQU    0x28    ; R/W, Baud rate divisor register  

; initial values for serial 
vULCON          EQU    0x3              ;ULCON = 0x3, No parity, One stop bit, 8 bits per frame
vUCON           EQU    0x245            ;UCON = 0x245, [11:10]=b00:select PCLK, [3:2]=b01:interrupt request or polling mode is selected as Transmit Mode, [1:0]=b01:interrupt request or polling mode is selected as Receive Mode
vUFCON          EQU    0x0              ;UFCON = 0, Non-FIFO mode
vUMCON          EQU    0x0              ;UMCON = 0, [4]=0:Disable Auto Flow Control, [0]=0:Inactivate nRTS





    END