tortola_memory_map_defines.h

i.MX31 NOR_flash(SPANSION_S71WS256ND0) bootloader src

//#########################################  
#define UART3_BASE_ADDR 0x5000C000 
#define UART3_URXD_3 (UART3_BASE_ADDR+0x00) //  32bit uart3 receiver reg
#define UART3_UTXD_3 (UART3_BASE_ADDR+0x40) //  32bit uart3 transmitter reg
#define UART3_UCR1_3 (UART3_BASE_ADDR+0x80) //  32bit uart3 control 1 reg
#define UART3_UCR2_3 (UART3_BASE_ADDR+0x84) //  32bit uart3 control 2 reg
#define UART3_UCR3_3 (UART3_BASE_ADDR+0x88) //  32bit uart3 control 3 reg
#define UART3_UCR4_3 (UART3_BASE_ADDR+0x8C) //  32bit uart3 control 4 reg
#define UART3_UFCR_3 (UART3_BASE_ADDR+0x90) //  32bit uart3 fifo control reg
#define UART3_USR1_3 (UART3_BASE_ADDR+0x94) //  32bit uart3 status 1 reg
#define UART3_USR2_3 (UART3_BASE_ADDR+0x98) //  32bit uart3 status 2 reg
#define UART3_UESC_3 (UART3_BASE_ADDR+0x9C) //  32bit uart3 escape char reg
#define UART3_UTIM_3 (UART3_BASE_ADDR+0xA0) //  32bit uart3 escape timer reg
#define UART3_UBIR_3 (UART3_BASE_ADDR+0xA4) //  32bit uart3 BRM incremental reg
#define UART3_UBMR_3 (UART3_BASE_ADDR+0xA8) //  32bit uart3 BRM modulator reg
#define UART3_UBRC_3 (UART3_BASE_ADDR+0xAC) //  32bit uart3 baud rate count reg
#define UART3_ONEMS_3 (UART3_BASE_ADDR+0xB0) //  32bit uart3 one ms reg
#define UART3_UTS_3 (UART3_BASE_ADDR+0xB4) //  32bit uart3 test reg
  
//#########################################  
//# UART4                                 #  
//# $43FB_0000 to $43FB_3FFF              #  
//#########################################  
#define UART4_BASE_ADDR 0x43FB0000 
#define UART4_URXD_4 (UART4_BASE_ADDR+0x00) //  32bit uart4 receiver reg
#define UART4_UTXD_4 (UART4_BASE_ADDR+0x40) //  32bit uart4 transmitter reg
#define UART4_UCR1_4 (UART4_BASE_ADDR+0x80) //  32bit uart4 control 1 reg
#define UART4_UCR2_4 (UART4_BASE_ADDR+0x84) //  32bit uart4 control 2 reg
#define UART4_UCR3_4 (UART4_BASE_ADDR+0x88) //  32bit uart4 control 3 reg
#define UART4_UCR4_4 (UART4_BASE_ADDR+0x8C) //  32bit uart4 control 4 reg
#define UART4_UFCR_4 (UART4_BASE_ADDR+0x90) //  32bit uart4 fifo control reg
#define UART4_USR1_4 (UART4_BASE_ADDR+0x94) //  32bit uart4 status 1 reg
#define UART4_USR2_4 (UART4_BASE_ADDR+0x98) //  32bit uart4 status 2 reg
#define UART4_UESC_4 (UART4_BASE_ADDR+0x9C) //  32bit uart4 escape char reg
#define UART4_UTIM_4 (UART4_BASE_ADDR+0xA0) //  32bit uart4 escape timer reg
#define UART4_UBIR_4 (UART4_BASE_ADDR+0xA4) //  32bit uart4 BRM incremental reg
#define UART4_UBMR_4 (UART4_BASE_ADDR+0xA8) //  32bit uart4 BRM modulator reg
#define UART4_UBRC_4 (UART4_BASE_ADDR+0xAC) //  32bit uart4 baud rate count reg
#define UART4_ONEMS_4 (UART4_BASE_ADDR+0xB0) //  32bit uart4 one ms reg
#define UART4_UTS_4 (UART4_BASE_ADDR+0xB4) //  32bit uart4 test reg
  
//#########################################  
//# UART5                                 #  
//# $43FB_4000 to $43FB_7FFF              #  
//#########################################  
#define UART5_BASE_ADDR 0x43FB4000 
#define UART5_URXD_5 (UART5_BASE_ADDR+0x00) //  32bit uart5 receiver reg
#define UART5_UTXD_5 (UART5_BASE_ADDR+0x40) //  32bit uart5 transmitter reg
#define UART5_UCR1_5 (UART5_BASE_ADDR+0x80) //  32bit uart5 control 1 reg
#define UART5_UCR2_5 (UART5_BASE_ADDR+0x84) //  32bit uart5 control 2 reg
#define UART5_UCR3_5 (UART5_BASE_ADDR+0x88) //  32bit uart5 control 3 reg
#define UART5_UCR4_5 (UART5_BASE_ADDR+0x8C) //  32bit uart5 control 4 reg
#define UART5_UFCR_5 (UART5_BASE_ADDR+0x90) //  32bit uart5 fifo control reg
#define UART5_USR1_5 (UART5_BASE_ADDR+0x94) //  32bit uart5 status 1 reg
#define UART5_USR2_5 (UART5_BASE_ADDR+0x98) //  32bit uart5 status 2 reg
#define UART5_UESC_5 (UART5_BASE_ADDR+0x9C) //  32bit uart5 escape char reg
#define UART5_UTIM_5 (UART5_BASE_ADDR+0xA0) //  32bit uart5 escape timer reg
#define UART5_UBIR_5 (UART5_BASE_ADDR+0xA4) //  32bit uart5 BRM incremental reg
#define UART5_UBMR_5 (UART5_BASE_ADDR+0xA8) //  32bit uart5 BRM modulator reg
#define UART5_UBRC_5 (UART5_BASE_ADDR+0xAC) //  32bit uart5 baud rate count reg
#define UART5_ONEMS_5 (UART5_BASE_ADDR+0xB0) //  32bit uart5 one ms reg
#define UART5_UTS_5 (UART5_BASE_ADDR+0xB4) //  32bit uart5 test reg
  
//#########################################  
//# USB_TOP                                #  
//# $43F8_8000 to $43F8_BFFF              #  
//#########################################  
//#**********************  
//#  USB MODULE  
//#**********************  
#define  USB_MODULE_BASE_ADDR 0x43F88000 
#define  USB_OTG_BASE_ADDR (USB_MODULE_BASE_ADDR + 0x000) 
#define  USB_H1_BASE_ADDR (USB_MODULE_BASE_ADDR + 0x200) 
#define  USB_H2_BASE_ADDR (USB_MODULE_BASE_ADDR + 0x400) 
#define  USB_CONTROL_REG (USB_MODULE_BASE_ADDR + 0x600) 
#define  USB_OTG_MIRROR_REG (USB_MODULE_BASE_ADDR + 0x604) 
  
//#**********************  
//# USB HOST 1  
//#**********************  
#define  USB_H1_ID (USB_H1_BASE_ADDR +0x000) //   Identification Register                
#define  USB_H1_HWGENERAL (USB_H1_BASE_ADDR +0x004) //   General Hardware Parameters            
#define  USB_H1_HWHOST (USB_H1_BASE_ADDR +0x008) //   Host Hardware Parameters               
#define  USB_H1_HWTXBUF (USB_H1_BASE_ADDR +0x010) //   TX Buffer Hardware Parameters          
#define  USB_H1_HWRXBUF (USB_H1_BASE_ADDR +0x014) //   RX Buffer Hardware Parameters          
#define  USB_H1_CAPLENGTH (USB_H1_BASE_ADDR +0x100) //   Capability Register Length             
#define  USB_H1_HCIVERSION (USB_H1_BASE_ADDR +0x102) //   Host Interface Version Number          
#define  USB_H1_HCSPARAMS (USB_H1_BASE_ADDR +0x104) //   Host Ctrl. Structural Parameters       
#define  USB_H1_HCCPARAMS (USB_H1_BASE_ADDR +0x108) //   Host Ctrl. Capability Parameters       
#define  USB_H1_USBCMD (USB_H1_BASE_ADDR +0x140) //   USB Command                            
#define  USB_H1_USBSTS (USB_H1_BASE_ADDR +0x144) //   USB Status                             
#define  USB_H1_USBINTR (USB_H1_BASE_ADDR +0x148) //   USB Interrupt Enable                   
#define  USB_H1_FRINDEX (USB_H1_BASE_ADDR +0x14C) //   USB Frame Index
#define  USB_H1_PERIODICLISTBASE (USB_H1_BASE_ADDR +0x154) //   Frame List Base Address                
#define  USB_H1_ASYNCLISTADDR (USB_H1_BASE_ADDR +0x158) //   Next Asynchronous List Address         
#define  USB_H1_BURSTSIZE (USB_H1_BASE_ADDR +0x160) //   Programmable Burst Size                
#define  USB_H1_TXFILLTUNING (USB_H1_BASE_ADDR +0x164) //   Host Transmit Pre-Buffer Packet Tuning 
#define  USB_H1_CONFIGFLAG (USB_H1_BASE_ADDR +0x180) //   Configured Flag Register               
#define  USB_H1_PORTSC1 (USB_H1_BASE_ADDR +0x184) //   Port Status/Control                    
#define  USB_H1_USBMODE (USB_H1_BASE_ADDR +0x1A8) //   USB Device Mode                        
  
//#**********************  
//# USB HOST 2  
//#**********************  
#define  USB_H2_ID (USB_H2_BASE_ADDR +0x000) //   Identification Register                
#define  USB_H2_HWGENERAL (USB_H2_BASE_ADDR +0x004) //   General Hardware Parameters            
#define  USB_H2_HWHOST (USB_H2_BASE_ADDR +0x008) //   Host Hardware Parameters               
#define  USB_H2_HWTXBUF (USB_H2_BASE_ADDR +0x010) //   TX Buffer Hardware Parameters          
#define  USB_H2_HWRXBUF (USB_H2_BASE_ADDR +0x014) //   RX Buffer Hardware Parameters          
#define  USB_H2_CAPLENGTH (USB_H2_BASE_ADDR +0x100) //   Capability Register Length             
#define  USB_H2_HCIVERSION (USB_H2_BASE_ADDR +0x102) //   Host Interface Version Number          
#define  USB_H2_HCSPARAMS (USB_H2_BASE_ADDR +0x104) //   Host Ctrl. Structural Parameters       
#define  USB_H2_HCCPARAMS (USB_H2_BASE_ADDR +0x108) //   Host Ctrl. Capability Parameters       
#define  USB_H2_USBCMD (USB_H2_BASE_ADDR +0x140) //   USB Command                            
#define  USB_H2_USBSTS (USB_H2_BASE_ADDR +0x144) //   USB Status                             
#define  USB_H2_USBINTR (USB_H2_BASE_ADDR +0x148) //   USB Interrupt Enable                   
#define  USB_H2_FRINDEX (USB_H2_BASE_ADDR +0x14C) //   USB Frame Index
#define  USB_H2_PERIODICLISTBASE (USB_H2_BASE_ADDR +0x154) //   Frame List Base Address                
#define  USB_H2_ASYNCLISTADDR (USB_H2_BASE_ADDR +0x158) //   Next Asynchronous List Address         
#define  USB_H2_BURSTSIZE (USB_H2_BASE_ADDR +0x160) //   Programmable Burst Size                
#define  USB_H2_TXFILLTUNING (USB_H2_BASE_ADDR +0x164) //   Host Transmit Pre-Buffer Packet Tuning 
#define  USB_H2_CONFIGFLAG (USB_H2_BASE_ADDR +0x180) //   Configured Flag Register               
#define  USB_H2_PORTSC1 (USB_H2_BASE_ADDR +0x184) //   Port Status/Control                    
#define  USB_H2_USBMODE (USB_H2_BASE_ADDR +0x1A8) //   USB Device Mode                        
  
//#*************  
//#   OTG  
//#*************  
#define  USB_OTG_ID (USB_OTG_BASE_ADDR + 0x000) //   Identification Register
#define  USB_OTG_HWGENERAL (USB_OTG_BASE_ADDR + 0x004) //   General Hardware Parameters
#define  USB_OTG_HWHOST (USB_OTG_BASE_ADDR + 0x008) //   Host Hardware Parameters
#define  USB_OTG_HWDEVICE (USB_OTG_BASE_ADDR + 0x00C) //   Device Hardware Parameters
#define  USB_OTG_HWTXBUF (USB_OTG_BASE_ADDR + 0x010) //   TX Buffer Hardware Parameters
#define  USB_OTG_HWRXBUF (USB_OTG_BASE_ADDR + 0x014) //   RX Buffer Hardware Parameters
#define  USB_OTG_CAPLENGTH (USB_OTG_BASE_ADDR + 0x100) //   Capability Register Length
#define  USB_OTG_HCIVERSION (USB_OTG_BASE_ADDR + 0x102) //   Host Interface Version Number
#define  USB_OTG_HCSPARAMS (USB_OTG_BASE_ADDR + 0x104) //   Host Ctrl. Structural Parameters
#define  USB_OTG_HCCPARAMS (USB_OTG_BASE_ADDR + 0x108) //   Host Ctrl. Capability Parameters
#define  USB_OTG_DCIVERSION (USB_OTG_BASE_ADDR + 0x120) //   Dev. Interface Version Number
#define  USB_OTG_DCCPARAMS (USB_OTG_BASE_ADDR + 0x124) //   Device Ctrl. Capability Parameters
  
#define  USB_OTG_USBCMD (USB_OTG_BASE_ADDR + 0x140) //   USB Command
#define  USB_OTG_USBSTS (USB_OTG_BASE_ADDR + 0x144) //   USB Status
#define  USB_OTG_USBINTR (USB_OTG_BASE_ADDR + 0x148) //   USB Interrupt Enable
#define  USB_OTG_FRINDEX (USB_OTG_BASE_ADDR+ 0x14C) //   USB Frame Index
#define  USB_OTG_PERIODICLISTBASE (USB_OTG_BASE_ADDR + 0x154) //   Frame List Base Address
//#      USB_OTG_Device Addr (USB_OTG_BASE_ADDR + 0x154) //   USB Device Address
#define  USB_OTG_ASYNCLISTADDR (USB_OTG_BASE_ADDR + 0x158) //   Next Asynchronous List Address
//#      USB_OTG_Endpointlist Addr (USB_OTG_BASE_ADDR + 0x158) //   Address at Endpoint list in memory
#define  USB_OTG_BURSTSIZE (USB_OTG_BASE_ADDR + 0x160) //   Programmable Burst Size
#define  USB_OTG_TXFILLTUNING (USB_OTG_BASE_ADDR + 0x164) //   Host Transmit Pre-Buffer Packet Tuning
#define  USB_OTG_CONFIGFLAG (USB_OTG_BASE_ADDR + 0x180) //   Configured Flag Register
#define  USB_OTG_PORTSC1 (USB_OTG_BASE_ADDR + 0x184) //   Port Status/Control  
#define  USB_OTG_OTGSC (USB_OTG_BASE_ADDR + 0x1A4) //   On-The-Go (OTG) Status and Control   
#define  USB_OTG_USBMODE (USB_OTG_BASE_ADDR + 0x1A8) //   USB Device Mode
#define  USB_OTG_ENPDTSETUPSTAT (USB_OTG_BASE_ADDR + 0x1AC) //   Endpoint Setup Status
#define  USB_OTG_ENDPTPRIME (USB_OTG_BASE_ADDR + 0x1B0) //   Endpoint Initialization
#define  USB_OTG_ENDPTFLUSH (USB_OTG_BASE_ADDR + 0x1B4) //   Endpoint De-Initialize
#define  USB_OTG_ENDPTSTATUS (USB_OTG_BASE_ADDR + 0x1B8) //   Endpoint Status
#define  USB_OTG_ENDPTCOMPLETE (USB_OTG_BASE_ADDR + 0x1BC) //   Endpoint Complete
#define  USB_OTG_ENDPTCTRL0 (USB_OTG_BASE_ADDR + 0x1C0) //   Endpoint Control 0
#define  USB_OTG_ENDPTCTRL1 (USB_OTG_BASE_ADDR + 0x1C4) //   Endpoint Control 1
#define  USB_OTG_ENDPTCTRL2 (USB_OTG_BASE_ADDR + 0x1C8) //   Endpoint Control 2
#define  USB_OTG_ENDPTCTRL3 (USB_OTG_BASE_ADDR + 0x1CC) //   Endpoint Control 3
#define  USB_OTG_ENDPTCTRL4 (USB_OTG_BASE_ADDR + 0x1D0) //   Endpoint Control 4
#define  USB_OTG_ENDPTCTRL5 (USB_OTG_BASE_ADDR + 0x1D4) //   Endpoint Control 5
#define  USB_OTG_ENDPTCTRL6 (USB_OTG_BASE_ADDR + 0x1D8) //   Endpoint Control 6
#define  USB_OTG_ENDPTCTRL7 (USB_OTG_BASE_ADDR + 0x1DC) //   Endpoint Control 7
  
//#########################################  
//# RTIC                                #  
//# $53FE_C000 to $53FE_FFFF              #  
//#########################################  
#define RTIC_BASE_ADDR 0x53FEC000 
#define RTIC_STATUS (RTIC_BASE_ADDR+0x000) //  base location for core
#define RTIC_COMMAND (RTIC_BASE_ADDR+0x004) //  base location for function
#define RTIC_CONTROL (RTIC_BASE_ADDR+0x008) //  base location for host
#define RTIC_DELAY_TIMER (RTIC_BASE_ADDR+0x00C) //  base location for dma
#define RTIC_MEMORYA_ADD1 (RTIC_BASE_ADDR+0x010) //  base location for dma
#define RTIC_MEMORYA_LEN1 (RTIC_BASE_ADDR+0x014) //  base location for dma
#define RTIC_MEMORYA_ADD2 (RTIC_BASE_ADDR+0x018) //  base location for dma
#define RTIC_MEMORYA_LEN2 (RTIC_BASE_ADDR+0x01C) //  base location for dma
  
  
#define RTIC_MEMORYB_ADD1 (RTIC_BASE_ADDR+0x030) //  base location for dma
#define RTIC_MEMORYB_LEN1 (RTIC_BASE_ADDR+0x034) //  base location for dma
#define RTIC_MEMORYB_ADD2 (RTIC_BASE_ADDR+0x038) //  base location for dma
#define RTIC_MEMORYB_LEN2 (RTIC_BASE_ADDR+0x03C) //  base location for dma
  
#define RTIC_MEMORYC_ADD1 (RTIC_BASE_ADDR+0x050) //  base location for dma
#define RTIC_MEMORYC_LEN1 (RTIC_BASE_ADDR+0x054) //  base location for dma
#define RTIC_MEMORYC_ADD2 (RTIC_BASE_ADDR+0x058) //  base location for dma
#define RTIC_MEMORYC_LEN2 (RTIC_BASE_ADDR+0x05C) //  base location for dma
  
#define RTIC_MEMORYD_ADD1 (RTIC_BASE_ADDR+0x070) //  base location for dma
#define RTIC_MEMORYD_LEN1 (RTIC_BASE_ADDR+0x074) //  base location for dma
#define RTIC_MEMORYD_ADD2 (RTIC_BASE_ADDR+0x078) //  base location for dma
#define RTIC_MEMORYD_LEN2 (RTIC_BASE_ADDR+0x07C) //  base location for dma
  
#define RTIC_FAULT_ADD (RTIC_BASE_ADDR+0x090) //  base location for dma
#define RTIC_WATCHDOG (RTIC_BASE_ADDR+0x094) //  base location for dma
  
#define RTIC_HASHA_128 (RTIC_BASE_ADDR+0x0A0) //  base location for dma
#define RTIC_HASHA_96 (RTIC_BASE_ADDR+0x0A4) //  base location for dma
#define RTIC_HASHA_64 (RTIC_BASE_ADDR+0x0A8) //  base location for dma
#define RTIC_HASHA_32 (RTIC_BASE_ADDR+0x0AC) //  base location for dma
#define RTIC_HASHA_0 (RTIC_BASE_ADDR+0x0B0) //  base location for dma
  
  
#define RTIC_HASHB_128 (RTIC_BASE_ADDR+0x0C0) //  base location for dma
#define RTIC_HASHB_96 (RTIC_BASE_ADDR+0x0C4) //  base location for dma
#define RTIC_HASHB_64 (RTIC_BASE_ADDR+0x0C8) //  base location for dma
#define RTIC_HASHB_32 (RTIC_BASE_ADDR+0x0CC) //  base location for dma
#define RTIC_HASHB_0 (RTIC_BASE_ADDR+0x0D0) //  base location for dma
  
  
#define RTIC_HASHC_128 (RTIC_BASE_ADDR+0x0E0) //  base location for dma
#define RTIC_HASHC_96 (RTIC_BASE_ADDR+0x0E4) //  base location for dma
#define RTIC_HASHC_64 (RTIC_BASE_ADDR+0x0E8) //  base location for dma
#define RTIC_HASHC_32 (RTIC_