tortola_memory_map_defines.h

i.MX31 NOR_flash(SPANSION_S71WS256ND0) bootloader src

#define WEIM_CS0A (WEIM_BASE_ADDR+0x08) 
#define WEIM_CS1U (WEIM_BASE_ADDR+0x10) 
#define WEIM_CS1L (WEIM_BASE_ADDR+0x14) 
#define WEIM_CS1A (WEIM_BASE_ADDR+0x18) 
#define WEIM_CS2U (WEIM_BASE_ADDR+0x20) 
#define WEIM_CS2L (WEIM_BASE_ADDR+0x24) 
#define WEIM_CS2A (WEIM_BASE_ADDR+0x28) 
#define WEIM_CS3U (WEIM_BASE_ADDR+0x30) 
#define WEIM_CS3L (WEIM_BASE_ADDR+0x34) 
#define WEIM_CS3A (WEIM_BASE_ADDR+0x38) 
#define WEIM_CS4U (WEIM_BASE_ADDR+0x40) 
#define WEIM_CS4L (WEIM_BASE_ADDR+0x44) 
#define WEIM_CS4A (WEIM_BASE_ADDR+0x48) 
#define WEIM_CS5U (WEIM_BASE_ADDR+0x50) 
#define WEIM_CS5L (WEIM_BASE_ADDR+0x54) 
#define WEIM_CS5A (WEIM_BASE_ADDR+0x58) 
#define WEIM_EIM (WEIM_BASE_ADDR+0x60) //  32bit eim configuration reg
  
//#########################################  
//# VRAM                                  #  
//# $1000_0000 to $1FFF_FFFF              #  
//#########################################  
#define VRAM_BASE_ADDR 0x10000000 //  vector ram (256b)
  
// ARM Program Status Register  
//  31  30  29  28  27  .........  7   6   5  4  3  2  1  0  
// ----------------------------------------------------------  
// | N | Z | C | V | Q |         | I | F | T |   M4 - M0    |  
// ----------------------------------------------------------  
  
//#########################################  
//# ARM MODES = {M4, M3, M2, M1, M0}      #  
//#########################################  
#define MODE_USR 0x10 
#define MODE_FIQ 0x11 
#define MODE_IRQ 0x12 
#define MODE_SVC 0x13 
#define MODE_ABT 0x17 
#define MODE_UND 0x1B 
#define MODE_SYS 0x1F 
#define MODE_BITS 0x1F 
  
//#########################################  
//# ARM INTERRUPTS                        #  
//#########################################  
#define INTERRUPT_BITS 0xC0 
#define ENABLE_IRQ 0x0 
#define ENABLE_FIQ 0x0 
#define DISABLE_FIQ 0x40 
#define DISABLE_IRQ 0x80 
  
//#########################################  
//# ARM CONDITION CODE FLAG = {N,Z,C,V,Q} #  
//#########################################  
#define FLAG_BITS 0xF8000000 
#define NFLAG 0x80000000 
#define ZFLAG 0x40000000 
#define CFLAG 0x20000000 
#define VFLAG 0x10000000 
#define QFLAG 0x08000000 

//#########################################  
//# For Stack at SDRAM0                   #  
//# SVC_STACK = C3FFFC00-C3FFFFFF (1kbyte)#  
//# IRQ_STACK = C3FFF800-C3FFFBFF (1kbyte)#  
//# FIQ_STACK = C3FFF400-C3FFF7FF (1kbyte)#  
//# USR_STACK = C3FFF000-C3FFF3FF (1kbyte)#  
//# UND_STACK = C3FFEC00-C3FFEFFF (1kbyte)#  
//#########################################  
#define SDRAM0_STACK 0x1FFFF000 //  stack at bottom os SDRAM0
#define SVC_SDRAM0_STACK SDRAM0_STACK 
#define IRQ_SDRAM0_STACK SDRAM0_STACK-0x0400 
#define FIQ_SDRAM0_STACK SDRAM0_STACK-0x0800 
#define USR_SDRAM0_STACK SDRAM0_STACK-0x0C00 
#define UND_SDRAM0_STACK SDRAM0_STACK-0x1000 
  
//#########################################  
//# For Stack at SDRAM1                   #  
//# SVC_STACK = C7FFFC00-C7FFFFFF (1kbyte)#  
//# IRQ_STACK = C7FFF800-C7FFFBFF (1kbyte)#  
//# FIQ_STACK = C7FFF400-C7FFF7FF (1kbyte)#  
//# USR_STACK = C7FFF000-C7FFF3FF (1kbyte)#  
//# UND_STACK = C7FFEC00-C7FFEFFF (1kbyte)#  
//#########################################  
#define SDRAM1_STACK 0x1FFFE000 //  stack at bottom os SDRAM1
#define SVC_SDRAM1_STACK SDRAM1_STACK 
#define IRQ_SDRAM1_STACK SDRAM1_STACK-0x0400 
#define FIQ_SDRAM1_STACK SDRAM1_STACK-0x0800 
#define USR_SDRAM1_STACK SDRAM1_STACK-0x0C00 
#define UND_SDRAM1_STACK SDRAM1_STACK-0x1000 
  
//#########################################  
//# For Stack at SRAM                     #  
//# SVC_STACK = CFFFFC00-CFFFFFFF (1kbyte)#  
//# IRQ_STACK = CFFFF800-CFFFFBFF (1kbyte)#  
//# FIQ_STACK = CFFFF400-CFFFF7FF (1kbyte)#  
//# USR_STACK = CFFFF000-CFFFF3FF (1kbyte)#  
//# UND_STACK = CFFFEC00-CFFFEFFF (1kbyte)#  
//#########################################  
#define SRAM_STACK 0x1FFFD000 //  stack at bottom os SRAM
#define SVC_SRAM_STACK SRAM_STACK 
#define IRQ_SRAM_STACK SRAM_STACK-0x0400 
#define FIQ_SRAM_STACK SRAM_STACK-0x0800 
#define USR_SRAM_STACK SRAM_STACK-0x0C00 
#define UND_SRAM_STACK SRAM_STACK-0x1000 
#define ABT_SRAM_STACK SRAM_STACK-0x1400 
#define SYS_SRAM_STACK SRAM_STACK-0x1800 
  
//#########################################  
//# GPIO  generic  
//# relative addresses  
//#########################################  
  
#define GPIO_DR0 0x00 //  32bit gpio pta data direction reg
#define GPIO_GDIR0 0x04 //  32bit gpio pta output config 1 reg
#define GPIO_PSR0 0x08 //  32bit gpio pta output config 2 reg
#define GPIO_ICR1 0x0C //  32bit gpio pta input config A1 reg
#define GPIO_ICR2 0x10 //  32bit gpio pta input config A2 reg
#define GPIO_IMR 0x14 //  32bit gpio pta input config B1 reg
#define GPIO_ISR 0x18 
  
//#########################################  
//# GPIO1                                #  
//# $53FCC000to $53FCFFFF             #  
//#########################################  
#define GPIO1_BASE_ADDR 0x53FCC000 
#define GPIO1_DR0 (GPIO1_BASE_ADDR+0x00) //  32bit gpio pta data direction reg
#define GPIO1_GDIR0 (GPIO1_BASE_ADDR+0x04) //  32bit gpio pta output config 1 reg
#define GPIO1_PSR0 (GPIO1_BASE_ADDR+0x08) //  32bit gpio pta output config 2 reg
#define GPIO1_ICR1 (GPIO1_BASE_ADDR+0x0C) //  32bit gpio pta input config A1 reg
#define GPIO1_ICR2 (GPIO1_BASE_ADDR+0x10) //  32bit gpio pta input config A2 reg
#define GPIO1_IMR (GPIO1_BASE_ADDR+0x14) //  32bit gpio pta input config B1 reg
#define GPIO1_ISR (GPIO1_BASE_ADDR+0x18) 
  
  
//#########################################  
//# CSPI   generic  
//# relative addresses  
//#########################################  
  
#define CSPI_RXDATA 0x00 //  32bit CSPI receive data reg
#define CSPI_TXDATA 0x04 //  32bit CSPI transmit data reg
#define CSPI_CONREG 0x08 //  32bit CSPI control reg
#define CSPI_INTREG 0x0C //  32bit CSPI interrupt stat/ctr reg
#define CSPI_DMAREG 0x10 //  32bit CSPI test reg
#define CSPI_STATREG 0x14 //  32bit CSPI sample period ctrl reg
#define CSPI_PERIODREG 0x18 //  32bit CSPI dma ctrl reg
#define CSPI_TESTREG 0x1C //  32bit CSPI soft reset reg
  
//#########################################  
//# CSPI1                                 #  
//# $43FA_4000 to $43FA_7FFF              #  
//#########################################  
#define CSPI1_BASE_ADDR 0x43FA4000 
#define CSPI1_RXDATA (CSPI1_BASE_ADDR+0x00) //  32bit cspi1 receive data reg
#define CSPI1_TXDATA (CSPI1_BASE_ADDR+0x04) //  32bit cspi1 transmit data reg
#define CSPI1_CONREG (CSPI1_BASE_ADDR+0x08) //  32bit cspi1 control reg
#define CSPI1_INTREG (CSPI1_BASE_ADDR+0x0C) //  32bit cspi1 interrupt stat/ctr reg
#define CSPI1_DMAREG (CSPI1_BASE_ADDR+0x10) //  32bit cspi1 test reg
#define CSPI1_STATREG (CSPI1_BASE_ADDR+0x14) //  32bit cspi1 sample period ctrl reg
#define CSPI1_PERIODREG (CSPI1_BASE_ADDR+0x18) //  32bit cspi1 dma ctrl reg
#define CSPI1_TESTREG (CSPI1_BASE_ADDR+0x1C) //  32bit cspi1 soft reset reg
  
//#########################################  
//# CSPI2                                 #  
//# $5001_0000 to $5001_3FFF              #  
//#########################################  
#define CSPI2_BASE_ADDR 0x50010000 
#define CSPI2_RXDATA (CSPI2_BASE_ADDR+0x00) //  32bit cspi2 receive data reg
#define CSPI2_TXDATA (CSPI2_BASE_ADDR+0x04) //  32bit cspi2 transmit data reg
#define CSPI2_CONREG (CSPI2_BASE_ADDR+0x08) //  32bit cspi2 control reg
#define CSPI2_INTREG (CSPI2_BASE_ADDR+0x0C) //  32bit cspi2 interrupt stat/ctr reg
#define CSPI2_DMAREG (CSPI2_BASE_ADDR+0x10) //  32bit cspi2 test reg
#define CSPI2_STATREG (CSPI2_BASE_ADDR+0x14) //  32bit cspi2 sample period ctrl reg
#define CSPI2_PERIODREG (CSPI2_BASE_ADDR+0x18) //  32bit cspi2 dma ctrl reg
#define CSPI2_TESTREG (CSPI2_BASE_ADDR+0x1C) //  32bit cspi2 soft reset reg
  
//#########################################  
//# CSPI3  
//# $53F8_4000 to $53F87FFF  
//#########################################  
#define CSPI3_BASE_ADDR 0x53F84000 
#define CSPI3_RXDATA (CSPI3_BASE_ADDR+0x00) //  32bit cspi3 receive data reg
#define CSPI3_TXDATA (CSPI3_BASE_ADDR+0x04) //  32bit cspi3 transmit data reg
#define CSPI3_CONREG (CSPI3_BASE_ADDR+0x08) //  32bit cspi3 control reg
#define CSPI3_INTREG (CSPI3_BASE_ADDR+0x0C) //  32bit cspi3 interrupt stat/ctr reg
#define CSPI3_DMAREG (CSPI3_BASE_ADDR+0x10) //  32bit cspi3 test reg
#define CSPI3_STATREG (CSPI3_BASE_ADDR+0x14) //  32bit cspi3 sample period ctrl reg
#define CSPI3_PERIODREG (CSPI3_BASE_ADDR+0x18) //  32bit cspi3 dma ctrl reg
#define CSPI3_TESTREG (CSPI3_BASE_ADDR+0x1C) //  32bit cspi3 soft reset reg
  
//#########################################  
//# OWIRE                                 #  
//# $43F9_C000 to $43F9_FFFF              #  
//#########################################  
#define OWIRE_BASE_ADDR 0x43F9C000 
#define OWIRE_CTRL (OWIRE_BASE_ADDR+0x00) //  16bit owire control reg
#define OWIRE_TIME_DIV (OWIRE_BASE_ADDR+0x02) //  16bit owire time divider reg
#define OWIRE_RESET (OWIRE_BASE_ADDR+0x04) //  16bit owire reset reg
  
//#########################################  
//# SDHC  generic  
//# relative addresses  
//#########################################  
#define SDHC_STR_STP_CLK 0x00 //  32bit SDHC control reg 
#define SDHC_STATUS 0x04 //  32bit SDHC status reg
#define SDHC_CLK_RATE 0x08 //  32bit SDHC clock rate reg
#define SDHC_CMD_DAT_CONT 0x0C //  32bit SDHC cmd/data control reg
#define SDHC_RESPONSE_TO 0x10 //  32bit SDHC response time out reg
#define SDHC_READ_TO 0x14 //  32bit SDHC read time out reg
#define SDHC_BLK_LEN 0x18 //  32bit SDHC block length reg
#define SDHC_NOB 0x1C //  32bit SDHC number of blocks reg
#define SDHC_REV_NO 0x20 //  32bit SDHC revision number reg
#define SDHC_INT_CNTR 0x24 //  32bit SDHC interrupt mask reg
#define SDHC_CMD 0x28 //  32bit SDHC command code reg
#define SDHC_ARG 0x2C //  32bit SDHC argument (high+low) reg
#define SDHC_RES_FIFO 0x34 //  32bit SDHC response fifo reg
#define SDHC_BUFFER_ACCESS 0x38 //  32bit SDHC buffer access reg
#define SDHC_REMAINING_NOB 0x40 //  32bit SDHC remaining NUM reg
#define SDHC_REMAINING_BLK_SIZE 0x44 //  32bit SDHC remaining block bytes  reg
  
//#########################################