tortola_memory_map_defines.h

i.MX31 NOR_flash(SPANSION_S71WS256ND0) bootloader src

#define CCM_LDC (CCM_BASE_ADDR+0x30) // 32bit Latch Divergence Counter Reg
#define CCM_DCVR0 (CCM_BASE_ADDR+0x34) // DPTC Comparator Value Reg 0
#define CCM_DCVR1 (CCM_BASE_ADDR+0x38) // DPTC Comparator Value Reg 1
#define CCM_DCVR2 (CCM_BASE_ADDR+0x3C) // DPTC Comparator Value Reg 2
#define CCM_DCVR3 (CCM_BASE_ADDR+0x40) // DPTC Comparator Value Reg 3
#define CCM_LTR0 (CCM_BASE_ADDR+0x44) // 32bit Load Tracking Reg 0
#define CCM_LTR1 (CCM_BASE_ADDR+0x48) // 32bit Load Tracking Reg 1
#define CCM_LTR2 (CCM_BASE_ADDR+0x4C) // 32bit Load Tracking Reg 2
#define CCM_LTR3 (CCM_BASE_ADDR+0x50) // 32bit Load Tracking Reg 3
#define CCM_LTBR0 (CCM_BASE_ADDR+0x54) // 32bit Load Tracking Buffer Reg 0
#define CCM_LTBR1 (CCM_BASE_ADDR+0x58) // 32bit Load Tracking Buffer Reg 1
#define CCM_PMCR0 (CCM_BASE_ADDR+0x5C) // 32bit Power Management Control Reg 0
#define CCM_PMCR1 (CCM_BASE_ADDR+0x60) // 32bit Power Management Control Reg 1
#define CCM_PDR2 (CCM_BASE_ADDR+0x64) //  32bit MCU PLL Control Reg
  
//#########################################  
//# FIRI                                  #  
//# $53F8_C000 to $53F8_FFFF              #  
//#########################################  
#define FIRI_BASE_ADDR 0x53F8C000 
#define FIRI_FIRITCR (FIRI_BASE_ADDR+0x00) //  32bit firi tx control reg 
#define FIRI_FIRITCTR (FIRI_BASE_ADDR+0x04) //  32bit firi tx count  reg
#define FIRI_FIRIRCR (FIRI_BASE_ADDR+0x08) //  32bit firi rx control reg
#define FIRI_FIRITSR (FIRI_BASE_ADDR+0x0C) //  32bit firi tx status reg
#define FIRI_FIRIRSR (FIRI_BASE_ADDR+0x10) //  32bit firi rx status reg
#define FIRI_TFIFO (FIRI_BASE_ADDR+0x14) //  32bit firi tx fifo reg
#define FIRI_RFIFO (FIRI_BASE_ADDR+0x18) //  32bit firi rx fifo reg
#define FIRI_FIRICR (FIRI_BASE_ADDR+0x1C) //  32bit firi control reg
  
//#########################################  
//# MAX                                   #  
//# $43F0_4000 to $43F0_7FFF               
//#########################################  
#define MAX_BASE_ADDR 0x43F04000 
#define MAX_SLV0_BASE (MAX_BASE_ADDR+0x000) //  base location for slave 0
#define MAX_SLV1_BASE (MAX_BASE_ADDR+0x100) //  base location for slave 1
#define MAX_SLV2_BASE (MAX_BASE_ADDR+0x200) //  base location for slave 2
#define MAX_SLV3_BASE (MAX_BASE_ADDR+0x300) //  base location for slave 3
#define MAX_SLV4_BASE (MAX_BASE_ADDR+0x400) //  base location for slave 3
#define MAX_SLV5_BASE (MAX_BASE_ADDR+0x500) //  base location for slave 3
#define MAX_SLV6_BASE (MAX_BASE_ADDR+0x600) //  base location for slave 3
#define MAX_SLV7_BASE (MAX_BASE_ADDR+0x700) //  base location for slave 3
  
#define MAX_SLV0_MPR0 (MAX_SLV0_BASE+0x00) //  32bit max slv0 master priority reg
#define MAX_SLV0_AMPR0 (MAX_SLV0_BASE+0x04) //  32bit max slv0 alt priority reg
#define MAX_SLV0_SGPCR0 (MAX_SLV0_BASE+0x10) //  32bit max slv0 general ctrl reg
#define MAX_SLV0_ASGPCR0 (MAX_SLV0_BASE+0x14) //  32bit max slv0 alt generl ctrl reg
  
#define MAX_SLV1_MPR1 (MAX_SLV1_BASE+0x00) //  32bit max slv1 master priority reg
#define MAX_SLV1_AMPR1 (MAX_SLV1_BASE+0x04) //  32bit max slv1 alt priority reg
#define MAX_SLV1_SGPCR1 (MAX_SLV1_BASE+0x10) //  32bit max slv1 general ctrl reg
#define MAX_SLV1_ASGPCR1 (MAX_SLV1_BASE+0x14) //  32bit max slv1 alt generl ctrl reg
  
#define MAX_SLV2_MPR2 (MAX_SLV2_BASE+0x00) //  32bit max slv2 master priority reg
#define MAX_SLV2_AMPR2 (MAX_SLV2_BASE+0x04) //  32bit max slv2 alt priority reg
#define MAX_SLV2_SGPCR2 (MAX_SLV2_BASE+0x10) //  32bit max slv2 general ctrl reg
#define MAX_SLV2_ASGPCR2 (MAX_SLV2_BASE+0x14) //  32bit max slv2 alt generl ctrl reg
  
#define MAX_SLV3_MPR3 (MAX_SLV3_BASE+0x00) //  32bit max slv3 master priority reg
#define MAX_SLV3_AMPR3 (MAX_SLV3_BASE+0x04) //  32bit max slv3 alt priority reg
#define MAX_SLV3_SGPCR3 (MAX_SLV3_BASE+0x10) //  32bit max slv3 general ctrl reg
#define MAX_SLV3_ASGPCR3 (MAX_SLV3_BASE+0x14) //  32bit max slv3 alt generl ctrl reg
  
#define MAX_SLV4_MPR4 (MAX_SLV4_BASE+0x00) //  32bit max slv3 master priority reg
#define MAX_SLV4_AMPR4 (MAX_SLV4_BASE+0x04) //  32bit max slv3 alt priority reg
#define MAX_SLV4_SGPCR4 (MAX_SLV4_BASE+0x10) //  32bit max slv3 general ctrl reg
#define MAX_SLV4_ASGPCR4 (MAX_SLV4_BASE+0x14) //  32bit max slv3 alt generl ctrl reg
  
#define MAX_SLV5_MPR5 (MAX_SLV5_BASE+0x00) //  32bit max slv3 master priority reg
#define MAX_SLV5_AMPR5 (MAX_SLV5_BASE+0x04) //  32bit max slv3 alt priority reg
#define MAX_SLV5_SGPCR5 (MAX_SLV5_BASE+0x10) //  32bit max slv3 general ctrl reg
#define MAX_SLV5_ASGPCR5 (MAX_SLV5_BASE+0x14) //  32bit max slv3 alt generl ctrl reg
  
#define MAX_SLV6_MPR6 (MAX_SLV6_BASE+0x00) //  32bit max slv3 master priority reg
#define MAX_SLV6_AMPR6 (MAX_SLV6_BASE+0x04) //  32bit max slv3 alt priority reg
#define MAX_SLV6_SGPCR6 (MAX_SLV6_BASE+0x10) //  32bit max slv3 general ctrl reg
#define MAX_SLV6_ASGPCR6 (MAX_SLV6_BASE+0x14) //  32bit max slv3 alt generl ctrl reg
  
#define MAX_SLV7_MPR7 (MAX_SLV7_BASE+0x00) //  32bit max slv3 master priority reg
#define MAX_SLV7_AMPR7 (MAX_SLV7_BASE+0x04) //  32bit max slv3 alt priority reg
#define MAX_SLV7_SGPCR7 (MAX_SLV7_BASE+0x10) //  32bit max slv3 general ctrl reg
#define MAX_SLV7_ASGPCR7 (MAX_SLV7_BASE+0x14) //  32bit max slv3 alt generl ctrl reg
  
#define MAX_MST0_MGPCR0 (MAX_BASE_ADDR+0x800) //  32bit max mst5 general ctrl reg
#define MAX_MST1_MGPCR1 (MAX_BASE_ADDR+0x900) //  32bit max mst5 general ctrl reg
#define MAX_MST2_MGPCR2 (MAX_BASE_ADDR+0xA00) //  32bit max mst5 general ctrl reg
#define MAX_MST3_MGPCR3 (MAX_BASE_ADDR+0xB00) //  32bit max mst5 general ctrl reg
#define MAX_MST4_MGPCR4 (MAX_BASE_ADDR+0xC00) //  32bit max mst5 general ctrl reg
#define MAX_MST5_MGPCR5 (MAX_BASE_ADDR+0xD00) //  32bit max mst5 general ctrl reg
#define MAX_MST6_MGPCR6 (MAX_BASE_ADDR+0xE00) //  32bit max mst5 general ctrl reg
#define MAX_MST7_MGPCR7 (MAX_BASE_ADDR+0xF00) //  32bit max mst5 general ctrl reg
  
//#########################################  
//# AVIC                                  #  
//# $6800_0000 to $6FFF_FFFF              #  
//#########################################  
#define AVIC_BASE_ADDR 0x68000000 
#define AVIC_INTCNTL (AVIC_BASE_ADDR+0x00) //  32bit AVIC int control reg
#define AVIC_NIMASK (AVIC_BASE_ADDR+0x04) //  32bit AVIC int mask reg
#define AVIC_INTENNUM (AVIC_BASE_ADDR+0x08) //  32bit AVIC int enable number reg
#define AVIC_INTDISNUM (AVIC_BASE_ADDR+0x0C) //  32bit AVIC int disable number reg
#define AVIC_INTENABLEH (AVIC_BASE_ADDR+0x10) //  32bit AVIC int enable reg high
#define AVIC_INTENABLEL (AVIC_BASE_ADDR+0x14) //  32bit AVIC int enable reg low
#define AVIC_INTTYPEH (AVIC_BASE_ADDR+0x18) //  32bit AVIC int type reg high
#define AVIC_INTTYPEL (AVIC_BASE_ADDR+0x1C) //  32bit AVIC int type reg low
#define AVIC_NIPRIORITY7 (AVIC_BASE_ADDR+0x20) //  32bit AVIC norm int priority lvl7
#define AVIC_NIPRIORITY6 (AVIC_BASE_ADDR+0x24) //  32bit AVIC norm int priority lvl6
#define AVIC_NIPRIORITY5 (AVIC_BASE_ADDR+0x28) //  32bit AVIC norm int priority lvl5
#define AVIC_NIPRIORITY4 (AVIC_BASE_ADDR+0x2C) //  32bit AVIC norm int priority lvl4
#define AVIC_NIPRIORITY3 (AVIC_BASE_ADDR+0x30) //  32bit AVIC norm int priority lvl3
#define AVIC_NIPRIORITY2 (AVIC_BASE_ADDR+0x34) //  32bit AVIC norm int priority lvl2
#define AVIC_NIPRIORITY1 (AVIC_BASE_ADDR+0x38) //  32bit AVIC norm int priority lvl1
#define AVIC_NIPRIORITY0 (AVIC_BASE_ADDR+0x3C) //  32bit AVIC norm int priority lvl0
#define AVIC_NIVECSR (AVIC_BASE_ADDR+0x40) //  32bit AVIC norm int vector/status
#define AVIC_FIVECSR (AVIC_BASE_ADDR+0x44) //  32bit AVIC fast int vector/status
#define AVIC_INTSRCH (AVIC_BASE_ADDR+0x48) //  32bit AVIC int source reg high
#define AVIC_INTSRCL (AVIC_BASE_ADDR+0x4C) //  32bit AVIC int source reg low
#define AVIC_INTFRCH (AVIC_BASE_ADDR+0x50) //  32bit AVIC int force reg high
#define AVIC_INTFRCL (AVIC_BASE_ADDR+0x54) //  32bit AVIC int force reg low
#define AVIC_NIPNDH (AVIC_BASE_ADDR+0x58) //  32bit AVIC norm int pending high
#define AVIC_NIPNDL (AVIC_BASE_ADDR+0x5C) //  32bit AVIC norm int pending low
#define AVIC_FIPNDH (AVIC_BASE_ADDR+0x60) //  32bit AVIC fast int pending high
#define AVIC_FIPNDL (AVIC_BASE_ADDR+0x64) //  32bit AVIC fast int pending low
  
//#########################################  
//# ROMPATCH                              #  
//# $6000_0000 to $67FF_FFFF              #  
//#########################################  
#define ROMPATCH_BASE_ADDR 0x60000000 
#define ROMPATCH_D15 (ROMPATCH_BASE_ADDR+0x0B4) //  32bit rompatch data reg 15
#define ROMPATCH_D14 (ROMPATCH_BASE_ADDR+0x0B8) //  32bit rompatch data reg 14
#define ROMPATCH_D13 (ROMPATCH_BASE_ADDR+0x0BC) //  32bit rompatch data reg 13
#define ROMPATCH_D12 (ROMPATCH_BASE_ADDR+0x0C0) //  32bit rompatch data reg 12
#define ROMPATCH_D11 (ROMPATCH_BASE_ADDR+0x0C4) //  32bit rompatch data reg 11
#define ROMPATCH_D10 (ROMPATCH_BASE_ADDR+0x0C8) //  32bit rompatch data reg 10
#define ROMPATCH_D9 (ROMPATCH_BASE_ADDR+0x0CC) //  32bit rompatch data reg 9
#define ROMPATCH_D8 (ROMPATCH_BASE_ADDR+0x0D0) //  32bit rompatch data reg 8
#define ROMPATCH_D7 (ROMPATCH_BASE_ADDR+0x0D4) //  32bit rompatch data reg 7
#define ROMPATCH_D6 (ROMPATCH_BASE_ADDR+0x0D8) //  32bit rompatch data reg 6
#define ROMPATCH_D5 (ROMPATCH_BASE_ADDR+0x0DC) //  32bit rompatch data reg 5
#define ROMPATCH_D4 (ROMPATCH_BASE_ADDR+0x0E0) //  32bit rompatch data reg 4
#define ROMPATCH_D3 (ROMPATCH_BASE_ADDR+0x0E4) //  32bit rompatch data reg 3
#define ROMPATCH_D2 (ROMPATCH_BASE_ADDR+0x0E8) //  32bit rompatch data reg 2
#define ROMPATCH_D1 (ROMPATCH_BASE_ADDR+0x0EC) //  32bit rompatch data reg 1
#define ROMPATCH_D0 (ROMPATCH_BASE_ADDR+0x0F0) //  32bit rompatch data reg 0
#define ROMPATCH_CNTL (ROMPATCH_BASE_ADDR+0x0F4) //  32bit rompatch control reg
#define ROMPATCH_ENH (ROMPATCH_BASE_ADDR+0x0F8) //  32bit rompatch enable reg high
#define ROMPATCH_ENL (ROMPATCH_BASE_ADDR+0x0FC) //  32bit rompatch enable reg low
#define ROMPATCH_A0 (ROMPATCH_BASE_ADDR+0x100) //  32bit rompatch addr reg 0
#define ROMPATCH_A1 (ROMPATCH_BASE_ADDR+0x104) //  32bit rompatch addr reg 1
#define ROMPATCH_A2 (ROMPATCH_BASE_ADDR+0x108) //  32bit rompatch addr reg 2
#define ROMPATCH_A3 (ROMPATCH_BASE_ADDR+0x10C) //  32bit rompatch addr reg 3
#define ROMPATCH_A4 (ROMPATCH_BASE_ADDR+0x110) //  32bit rompatch addr reg 4
#define ROMPATCH_A5 (ROMPATCH_BASE_ADDR+0x114) //  32bit rompatch addr reg 5
#define ROMPATCH_A6 (ROMPATCH_BASE_ADDR+0x118) //  32bit rompatch addr reg 6
#define ROMPATCH_A7 (ROMPATCH_BASE_ADDR+0x11C) //  32bit rompatch addr reg 7
#define ROMPATCH_A8 (ROMPATCH_BASE_ADDR+0x120) //  32bit rompatch addr reg 8
#define ROMPATCH_A9 (ROMPATCH_BASE_ADDR+0x124) //  32bit rompatch addr reg 9
#define ROMPATCH_A10 (ROMPATCH_BASE_ADDR+0x128) //  32bit rompatch addr reg 10
#define ROMPATCH_A11 (ROMPATCH_BASE_ADDR+0x12C) //  32bit rompatch addr reg 11
#define ROMPATCH_A12 (ROMPATCH_BASE_ADDR+0x130) //  32bit rompatch addr reg 12
#define ROMPATCH_A13 (ROMPATCH_BASE_ADDR+0x134) //  32bit rompatch addr reg 13
#define ROMPATCH_A14 (ROMPATCH_BASE_ADDR+0x138) //  32bit rompatch addr reg 14
#define ROMPATCH_A15 (ROMPATCH_BASE_ADDR+0x13C) //  32bit rompatch addr reg 15
#define ROMPATCH_A16 (ROMPATCH_BASE_ADDR+0x140) //  32bit rompatch addr reg 16
#define ROMPATCH_A17 (ROMPATCH_BASE_ADDR+0x144) //  32bit rompatch addr reg 17
#define ROMPATCH_A18 (ROMPATCH_BASE_ADDR+0x148) //  32bit rompatch addr reg 18
#define ROMPATCH_A19 (ROMPATCH_BASE_ADDR+0x14C) //  32bit rompatch addr reg 19
#define ROMPATCH_A20 (ROMPATCH_BASE_ADDR+0x150) //  32bit rompatch addr reg 20
#define ROMPATCH_A21 (ROMPATCH_BASE_ADDR+0x154) //  32bit rompatch addr reg 21
#define ROMPATCH_A22 (ROMPATCH_BASE_ADDR+0x158) //  32bit rompatch addr reg 22
#define ROMPATCH_A23 (ROMPATCH_BASE_ADDR+0x15C) //  32bit rompatch addr reg 23
#define ROMPATCH_A24 (ROMPATCH_BASE_ADDR+0x160) //  32bit rompatch addr reg 24
#define ROMPATCH_A25 (ROMPATCH_BASE_ADDR+0x164) //  32bit rompatch addr reg 25
#define ROMPATCH_A26 (ROMPATCH_BASE_ADDR+0x168) //  32bit rompatch addr reg 26
#define ROMPATCH_A27 (ROMPATCH_BASE_ADDR+0x16C) //  32bit rompatch addr reg 27
#define ROMPATCH_A28 (ROMPATCH_BASE_ADDR+0x170) //  32bit rompatch addr reg 28
#define ROMPATCH_A29 (ROMPATCH_BASE_ADDR+0x174) //  32bit rompatch addr reg 29
#define ROMPATCH_A30 (ROMPATCH_BASE_ADDR+0x178) //  32bit rompatch addr reg 30
#define ROMPATCH_A31 (ROMPATCH_BASE_ADDR+0x17C) //  32bit rompatch addr reg 31
#define ROMPATCH_BRPT (ROMPATCH_BASE_ADDR+0x200) //  32bit rompatch 
#define ROMPATCH_BASE (ROMPATCH_BASE_ADDR+0x204) //  32bit rompatch base addr reg
#define ROMPATCH_SR (ROMPATCH_BASE_ADDR+0x208) //  32bit rompatch status reg
#define ROMPATCH_ABSR (ROMPATCH_BASE_ADDR+0x20C) //  32bit rompatch abort status reg
#define ROMPATCH_DADR (ROMPATCH_BASE_ADDR+0x210) //  32bit rompatch d-ahb addr abort
#define ROMPATCH_IADR (ROMPATCH_BASE_ADDR+0x214) //  32bit rompatch i-ahb addr abort
  
//#########################################  
//# $8000_0000 to $8FFF_FFFF (CSD0)        #  
//# $9000_0000 to $9FFF_FFFF (CSD1)        #  
//# $A000_0000 to $A7FF_FFFF (CS0)        #  
//# $A800_0000 to $AFFF_FFFF (CS1)        #  
//# $8000_0000 to $81FF_FFFF (CS2)        #  
//# $8200_0000 to $83FF_FFFF (CS3)        #  
//# $8400_0000 to $85FF_FFFF (CS4)        #  
//# $8600_0000 to $87FF_FFFF (CS5)        #  
//#########################################  
//#########################################  
#define CS0_BASE_ADDR 0xA0000000 //  CS0 (64Mb)
#define CS0_END_ADDR 0xA7FFFFFF 
#define CS1_BASE_ADDR 0xA8000000 //  CS1 (64Mb)
#define CS1_END_ADDR 0xAFFFFFFF 
#define CS2_BASE_ADDR 0xB0000000 //  CS2 (16Mb)
#define CS2_END_ADDR 0xB1FFFFFF 
#define CS3_BASE_ADDR 0xB2000000 //  CS3 (16Mb)
#define CS3_END_ADDR 0xB3FFFFFF 
#define CS4_BASE_ADDR 0xB4000000 //  CS4 (16Mb)
#define CS4_END_ADDR 0xB5FFFFFF 
#define CS5_BASE_ADDR 0xB6000000 //  CS5 (16Mb)
#define CS5_END_ADDR 0xB7FFFFFF 
#define CSD0_BASE_ADDR 0x80000000 //   CSD0
#define CSD0_END_ADDR 0x8FFFFFFF 
#define CSD1_BASE_ADDR 0x90000000 //   CSD1
#define CSD1_END_ADDR 0x9FFFFFFF 
  
//#########################################  
//# WEIM                                  #  
//# $B800_2000 to $B800_2FFF              #  
//#########################################  
#define WEIM_BASE_ADDR 0xB8002000 
#define WEIM_CS0U (WEIM_BASE_ADDR+0x00) 
#define WEIM_CS0L (WEIM_BASE_ADDR+0x04)