tortola_memory_map_defines.h

i.MX31 NOR_flash(SPANSION_S71WS256ND0) bootloader src

//############################################################################  
//#                                                                            
//#                    Tortola specific memory map                     
//#                     Motorola Confidential Proprietary                      
//# Purpose:                                                                   
//#   This file is used by the ARM GAS, ARM GCC and verilog Simulator    
//#        to decode the memory map                                                                      
//# Description                                                                
//#   This file list out each individual memory location for decoding          
//#                                                                            
//# Initial version writen By                                                  
//#   Shiri Earon  ([e-mail]) SPS                              
//#                                                                            
//# Date                                                                       
//# 27 Mar 2003                                                                
//#                                                                            
//# Revisions                                                                  
//#                                                                            
//############################################################################  
  
//#include "/vobs/vb_msil_ws_designs/iomuxc/iomuxc_tortola/iomuxc/testbench/defines_v/iomuxc_mem_map.h" 
#include "iomuxc_mem_map.h" 

//#########################################  
//# BOOT ROM                              #  
//# $0000_0000 to $0000_3FFF              #  
//#########################################  
#define BOOTROM1_ADDR_BOT 0x00000000 //  boot rom section 1 bottom address
#define BOOTROM1_PHY_SIZE 0x00008000 //  boot rom section 1 physical size
#define BOOTROM1_ASS_SIZE 0x00004000 //  boot rom section 1 assigned size
  
//#########################################  
//# AIPS1                                 #  
//# $43F0_0000 to $43F0_3FFF              #  
//#########################################  
#define AIPS1_BASE_ADDR 0x43F00000 
#define AIPS1_MPROT0_7 (AIPS1_BASE_ADDR+0x00) //  32bit Peripheral Size Reg 0
#define AIPS1_MPROT8_15 (AIPS1_BASE_ADDR+0x04) //  32bit Peripheral Size Reg 1
#define AIPS1_PACR0_7 (AIPS1_BASE_ADDR+0x20) //  32bit Peripheral Access Reg
#define AIPS1_PACR8_15 (AIPS1_BASE_ADDR+0x24) //  32bit Peripheral Access Reg
#define AIPS1_PACR16_23 (AIPS1_BASE_ADDR+0x28) //  32bit Peripheral Access Reg
#define AIPS1_PACR24_31 (AIPS1_BASE_ADDR+0x2C) //  32bit Peripheral Access Reg
#define AIPS1_OPACR0_7 (AIPS1_BASE_ADDR+0x40) //  32bit Peripheral Access Reg
#define AIPS1_OPACR8_15 (AIPS1_BASE_ADDR+0x44) //  32bit Peripheral Access Reg
#define AIPS1_OPACR16_23 (AIPS1_BASE_ADDR+0x48) //  32bit Peripheral Access Reg
#define AIPS1_OPACR24_31 (AIPS1_BASE_ADDR+0x4C) //  32bit Peripheral Access Reg
#define AIPS1_OPACR32_33 (AIPS1_BASE_ADDR+0x50) //  32bit Peripheral Access Reg
  
//#########################################  
//# AIPS Generic   
//# relative addresses            
//#########################################  
  
#define AIPS_MPROT0_7 0x00 //  32bit Peripheral Size Reg 0
#define AIPS_MPROT8_15 0x04 //  32bit Peripheral Size Reg 1
#define AIPS_PACR0_7 0x20 //  32bit Peripheral Access Reg
#define AIPS_PACR8_15 0x24 //  32bit Peripheral Access Reg
#define AIPS_PACR16_23 0x28 //  32bit Peripheral Access Reg
#define AIPS_PACR24_31 0x2C //  32bit Peripheral Access Reg
#define AIPS_OPACR0_7 0x40 //  32bit Peripheral Access Reg
#define AIPS_OPACR8_15 0x44 //  32bit Peripheral Access Reg
#define AIPS_OPACR16_23 0x48 //  32bit Peripheral Access Reg
#define AIPS_OPACR24_31 0x4C //  32bit Peripheral Access Reg
#define AIPS_OPACR32_33 0x50 //  32bit Peripheral Access Reg
  
//#########################################  
//# WDOG                                  #  
//# $53FD_C000 to $53FD_FFFF              #  
//#########################################  
#define WDOG_BASE_ADDR 0x53FDC000 
#define WDOG_WCR (WDOG_BASE_ADDR+0x00) //  16bit watchdog control reg
#define WDOG_WSR (WDOG_BASE_ADDR+0x02) //  16bit watchdog service reg
#define WDOG_WRSR (WDOG_BASE_ADDR+0x04) //  16bit watchdog reset status reg
  
//#########################################  
//# GPT  
//# $53F9_0000 to $53F9_3FFF              #  
//#########################################  
#define GPT_BASE_ADDR 0x53F90000 
#define GPT_GPTCR (GPT_BASE_ADDR+0x00) //  32bit timer 1 control reg
#define GPT_GPTPR (GPT_BASE_ADDR+0x04) //  32bit timer 1 prescaler reg
#define GPT_GPTSR (GPT_BASE_ADDR+0x08) //  32bit timer 1 compare reg
#define GPT_GPTIR (GPT_BASE_ADDR+0x0C) //  32bit timer 1 capture reg
#define GPT_GPTOCR1 (GPT_BASE_ADDR+0x10) //  32bit timer 1 counter reg
#define GPT_GPTOCR2 (GPT_BASE_ADDR+0x14) //  32bit timer 1 status reg
#define GPT_GPTOCR3 (GPT_BASE_ADDR+0x18) 
#define GPT_GPTICR1 (GPT_BASE_ADDR+0x1C) 
#define GPT_GPTICR2 (GPT_BASE_ADDR+0x20) 
#define GPT_GPTCNT (GPT_BASE_ADDR+0x24) 

//#########################################  
//# EPIT1                                  #  
//# $53F9_4000 to $53F9_7FFF              #  
//#########################################  
#define EPIT1_BASE_ADDR 0x53F94000 
#define EPIT1_EPITCR (EPIT1_BASE_ADDR+0x00) //  32bit timer 2 control reg
#define EPIT1_EPITSR (EPIT1_BASE_ADDR+0x04) //  32bit timer 2 prescaler reg
#define EPIT1_EPITLR (EPIT1_BASE_ADDR+0x08) //  32bit timer 2 compare reg
#define EPIT1_EPITCMPR (EPIT1_BASE_ADDR+0x0C) //  32bit timer 2 capture reg
#define EPIT1_EPITCNR (EPIT1_BASE_ADDR+0x10) //  32bit timer 2 counter reg
  
//#########################################  
//# EPIT2                                  #  
//# $53F9_8000 to $53F9_BFFF              #  
//#########################################  
#define EPIT2_BASE_ADDR 0x53F98000 
#define EPIT2_EPITCR (EPIT2_BASE_ADDR+0x00) //  32bit timer 3 control reg
#define EPIT2_EPITSR (EPIT2_BASE_ADDR+0x04) //  32bit timer 3 prescaler reg
#define EPIT2_EPITLR (EPIT2_BASE_ADDR+0x08) //  32bit timer 3 compare reg
#define EPIT2_EPITCMPR (EPIT2_BASE_ADDR+0x0C) //  32bit timer 3 capture reg
#define EPIT2_EPITCNR (EPIT2_BASE_ADDR+0x10) //  32bit timer 3 counter reg
  
//#########################################  
//# EPIT generic   
//# relative addresses  
//#########################################  
  
#define EPIT_EPITCR 0x00 //  32bit timer 3 control reg
#define EPIT_EPITSR 0x04 //  32bit timer 3 prescaler reg
#define EPIT_EPITLR 0x08 //  32bit timer 3 compare reg
#define EPIT_EPITCMPR 0x0C //  32bit timer 3 capture reg
#define EPIT_EPITCNR 0x10 //  32bit timer 3 counter reg
  
//#########################################  
//# PWM                                   #  
//# $53FE_0000 to $53FE_3FFF              #  
//#########################################  
#define PWM_BASE_ADDR 0x53FE0000 
#define PWM_PWMCR (PWM_BASE_ADDR+0x00) //  32bit pwm control reg
#define PWM_PWMSR (PWM_BASE_ADDR+0x04) //  32bit pwm sample reg
#define PWM_PWMIR (PWM_BASE_ADDR+0x08) //  32bit pwm period reg
#define PWM_PWMSAR (PWM_BASE_ADDR+0x0C) //  32bit pwm counter reg
#define PWM_PWMPR (PWM_BASE_ADDR+0x10) //  32bit pwm test reg
#define PWM_PWMCNR (PWM_BASE_ADDR+0x14) 
  
//#########################################  
//# RTC                                   #  
//# $53FD_8000 to $53FD_BFFF              #  
//#########################################  
#define RTC_BASE_ADDR 0x53FD8000 
#define RTC_HOURMIN (RTC_BASE_ADDR+0x00) //  32bit rtc hour/min counter reg
#define RTC_SECOND (RTC_BASE_ADDR+0x04) //  32bit rtc seconds counter reg
#define RTC_ALRM_HM (RTC_BASE_ADDR+0x08) //  32bit rtc alarm hour/min reg
#define RTC_ALRM_SEC (RTC_BASE_ADDR+0x0C) //  32bit rtc alarm seconds reg
#define RTC_RTCCTL (RTC_BASE_ADDR+0x10) //  32bit rtc control reg
#define RTC_RTCISR (RTC_BASE_ADDR+0x14) //  32bit rtc interrupt status reg
#define RTC_RTCIENR (RTC_BASE_ADDR+0x18) //  32bit rtc interrupt enable reg
#define RTC_STPWCH (RTC_BASE_ADDR+0x1C) //  32bit rtc stopwatch min reg
#define RTC_DAYR (RTC_BASE_ADDR+0x20) //  32bit rtc days counter reg
#define RTC_DAYALARM (RTC_BASE_ADDR+0x24) //  32bit rtc day alarm reg
#define RTC_TEST1 (RTC_BASE_ADDR+0x28) //  32bit rtc test reg 1
#define RTC_TEST2 (RTC_BASE_ADDR+0x2C) //  32bit rtc test reg 2
#define RTC_TEST3 (RTC_BASE_ADDR+0x30) //  32bit rtc test reg 3
  
//#########################################  
//# KPP                                   #  
//# $43FA_8000 to $43FA_BFFF           #  
//#########################################  
#define KPP_BASE_ADDR 0x43FA8000 
#define KPP_KPCR (KPP_BASE_ADDR+0x00) //  16bit kpp keypad control reg
#define KPP_KPSR (KPP_BASE_ADDR+0x02) //  16bit kpp keypad status reg
#define KPP_KDDR (KPP_BASE_ADDR+0x04) //  16bit kpp keypad data directon reg
#define KPP_KPDR (KPP_BASE_ADDR+0x06) //  16bit kpp keypad data reg
  
//#########################################  
//# I2C1                                   #  
//# $43F8_0000 to $43F8_3FFF              #  
//#########################################  
#define I2C1_BASE_ADDR 0x43F80000 
#define I2C1_IADR (I2C1_BASE_ADDR+0x00) //  16bit i2c address reg
#define I2C1_IFDR (I2C1_BASE_ADDR+0x04) //  16bit i2c frequency divider reg
#define I2C1_I2CR (I2C1_BASE_ADDR+0x08) //  16bit i2c control reg
#define I2C1_I2SR (I2C1_BASE_ADDR+0x0C) //  16bit i2c status reg
#define I2C1_I2DR (I2C1_BASE_ADDR+0x10) //  16bit i2c data i/o reg
  
//#########################################  
//# I2C generic  
//# relative addresses  
//#########################################  
  
#define I2C_IADR 0x00 //  16bit i2c address reg
#define I2C_IFDR 0x04 //  16bit i2c frequency divider reg
#define I2C_I2CR 0x08 //  16bit i2c control reg
#define I2C_I2SR 0x0C //  16bit i2c status reg
#define I2C_I2DR 0x10 //  16bit i2c data i/o reg
  
//#########################################  
//# AIPS2                                 #  
//# $43F0_0000 to $43F0_3FFF              #  
//#########################################  
#define AIPS2_BASE_ADDR 0x53F00000 
#define AIPS2_MPROT0_7 (AIPS2_BASE_ADDR+0x00) //  32bit Peripheral Size Reg 0
#define AIPS2_MPROT8_15 (AIPS2_BASE_ADDR+0x04) //  32bit Peripheral Size Reg 1
#define AIPS2_PACR0_7 (AIPS2_BASE_ADDR+0x20) //  32bit Peripheral Access Reg
#define AIPS2_PACR8_15 (AIPS2_BASE_ADDR+0x24) //  32bit Peripheral Access Reg
#define AIPS2_PACR16_23 (AIPS2_BASE_ADDR+0x28) //  32bit Peripheral Access Reg
#define AIPS2_PACR24_31 (AIPS2_BASE_ADDR+0x2C) //  32bit Peripheral Access Reg
#define AIPS2_OPACR0_7 (AIPS2_BASE_ADDR+0x40) //  32bit Peripheral Access Reg
#define AIPS2_OPACR8_15 (AIPS2_BASE_ADDR+0x44) //  32bit Peripheral Access Reg
#define AIPS2_OPACR16_23 (AIPS2_BASE_ADDR+0x48) //  32bit Peripheral Access Reg
#define AIPS2_OPACR24_31 (AIPS2_BASE_ADDR+0x4C) //  32bit Peripheral Access Reg
#define AIPS2_OPACR32_33 (AIPS2_BASE_ADDR+0x50) //  32bit Peripheral Access Reg
  
  
//#########################################  
//# Clock  Reset (CCM)                   #  
//# System control                        #  
//# $53F8_0000 to $53F8_3FFF              #  
//#########################################  
#define CCM_BASE_ADDR 0x53F80000 
#define CCM_CCMR (CCM_BASE_ADDR+0x00) //  32bit Clock Source Control Reg
#define CCM_PDR0 (CCM_BASE_ADDR+0x04) //  32bit MCU PLL Control Reg
#define CCM_PDR1 (CCM_BASE_ADDR+0x08) //  32bit MCU PLL Control Reg
#define CCM_RCSR (CCM_BASE_ADDR+0x0C) //  32bit MCU PLL Control Reg
#define CCM_MPCTL (CCM_BASE_ADDR+0x10) //  32bit Serial Perpheral PLL Ctrl 0
#define CCM_UPCTL (CCM_BASE_ADDR+0x14) //  32bit Serial Perpheral PLL Ctrl 1
#define CCM_SPCTL (CCM_BASE_ADDR+0x18) //  32bit Serial Perpheral PLL Ctrl 1
#define CCM_COSR (CCM_BASE_ADDR+0x1C) //  32bit Osc 26M register
#define CCM_CGR0 (CCM_BASE_ADDR+0x20) //  32bit Serial Perpheral Clk Div Reg
#define CCM_CGR1 (CCM_BASE_ADDR+0x24) //  32bit Perpheral Clk Control Reg 0
#define CCM_CGR2 (CCM_BASE_ADDR+0x28) //  32bit Perpheral Clk Control Reg 0
#define CCM_WIMR (CCM_BASE_ADDR+0x2C) //  32bit Wake-up Interrupt Mask Reg