init.s

i.MX31 NOR_flash(SPANSION_S71WS256ND0) bootloader src

        AREA    Init, CODE, READONLY

; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UNDEF      EQU     0x1B
Mode_SYS        EQU     0x1F ; available on ARM Arch 4 and later

I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled

; --- Amount of memory (in bytes) allocated for stacks

; --- Amount of memory (in bytes) allocated for stacks

Len_FIQ_Stack    EQU     1024
Len_IRQ_Stack    EQU     1024
Len_ABT_Stack    EQU     1024
Len_UND_Stack    EQU     1024
Len_SVC_Stack    EQU     1024
Len_USR_Stack    EQU     1024


; Add lengths >0 for FIQ_Stack, ABT_Stack, UND_Stack if you need them.
; Offsets will be loaded as immediate values.
; Offsets must be 8 byte aligned.

Offset_FIQ_Stack         EQU     0
Offset_IRQ_Stack         EQU     Offset_FIQ_Stack + Len_FIQ_Stack
Offset_ABT_Stack         EQU     Offset_IRQ_Stack + Len_IRQ_Stack
Offset_UND_Stack         EQU     Offset_ABT_Stack + Len_ABT_Stack
Offset_SVC_Stack         EQU     Offset_UND_Stack + Len_UND_Stack
Offset_USR_Stack         EQU     Offset_SVC_Stack + Len_SVC_Stack

        ENTRY

        EXPORT  Reset_Handler

Reset_Handler

; --- Initialize stack pointer registers

; Enter each mode in turn and set up the stack pointer

       IMPORT  top_of_stacks       ; defined in stack.s and located by scatter file
       LDR     sp, =top_of_stacks

       MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
	   LDR     sp, =top_of_stacks + Offset_FIQ_Stack

       MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
	   LDR     sp, =top_of_stacks + Offset_IRQ_Stack

       MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts
       LDR     sp, =top_of_stacks + Offset_ABT_Stack

;       MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts

       MSR     CPSR_c, #Mode_SVC;  Interrupts enabled
       LDR     sp, =top_of_stacks + Offset_SVC_Stack

; initial SPBA to enable all 3 masters      
	LDR r1, =0x5003C000
	LDR r2, =0x00000007
	STR r2, [r1]	
	LDR r1, =0x5003C004
	LDR r2, =0x00000007
	STR r2, [r1]	
	LDR r1, =0x5003C008
	LDR r2, =0x00000007
	STR r2, [r1]	
	LDR r1, =0x5003C00C
	LDR r2, =0x00000007
	STR r2, [r1]	
	LDR r1, =0x5003C010
	LDR r2, =0x00000007
	STR r2, [r1]	
	LDR r1, =0x5003C014
	LDR r2, =0x00000007
	STR r2, [r1]	
	LDR r1, =0x5003C018
	LDR r2, =0x00000007
	STR r2, [r1]	
	LDR r1, =0x5003C01C
	LDR r2, =0x00000007
	STR r2, [r1]	
	LDR r1, =0x5003C020
	LDR r2, =0x00000007
	STR r2, [r1]	
	LDR r1, =0x5003C024
	LDR r2, =0x00000007
	STR r2, [r1]	
	LDR r1, =0x5003C028
	LDR r2, =0x00000007
	STR r2, [r1]	
	LDR r1, =0x5003C02C
	LDR r2, =0x00000007
	STR r2, [r1]	
	LDR r1, =0x5003C030
	LDR r2, =0x00000007
	STR r2, [r1]	
	LDR r1, =0x5003C034
	LDR r2, =0x00000007
	STR r2, [r1]	
	LDR r1, =0x5003C038
	LDR r2, =0x00000007
	STR r2, [r1]
; 

; --- Initialize critical IO devices

	;enable AVIC access
	ldr     r1, =0x40000015
	mcr     p15,0,r1,c15,c2,0x4
	nop
	nop
	nop
	nop

; --- Now change to User mode and set up User mode stack, if needed
;        MSR     CPSR_c, #Mode_USR:OR:I_Bit:OR:F_Bit ; No interrupts
;        SUB     sp, r0, #Offset_USR_Stack
; @@@@@@@@ clear the Scc interrupt
;WAIT_FOR_ZEROIZING
;    LDR r0, =0x53FAC010  ; SCM_STATUS
;    LDR r1, =0x00000200
;    LDR r2, [r0]
;    AND r2,r2,r1
;    cmp r2,r1
;    bne WAIT_FOR_ZEROIZING
; 
;    LDR      r0, =0x53FAC018 ; SCM_INT_CONTROL
;    LDR      r1, [r0]
;    LDR      r2, =0x00000002
;    ORR      r2, r2, r1 
;    STR      r2, [r0]
     
    ldr r1, =0x68000010  ; AVIC_INTENABLEH/L
    ldr r0, =0xffffffff  ; enable all int but scc
    str r0,[r1,#4]
    bic  r0,r0,#0x20000        ; scc is int 49 i.e. 17 in INTENABLEH
    str r0,[r1,#0]

    
        LDR    r1,    =0x53F80004  ; CCM_MPDR0
        LDR    r2,     [r1,#0x0] 
        LDR    r3,    =0xfffffff8
        AND    r2,r2,r3
        STR    r2,     [r1,#0x0] 
                
    IMPORT  __main

; --- Now enter the C code
    B       __main   ; note use B not BL, because an application will never return this way

    END