📄 datagenerate.rpt
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| | | | | | | | | | | | | | | +- LC20 :147
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC23 -> * * * * - - - - - - - - - - * - | - * | <-- DataBus0
LC24 -> - * * * - - - - - - - - - - * - | - * | <-- DataBus1
LC22 -> - - * * - - - - - - - - - - * - | - * | <-- DataBus2
LC17 -> - - - * - - - - - - - - - - * - | - * | <-- DataBus3
LC18 -> - - - - * * * - - - - - - - - * | - * | <-- DataBus4
LC19 -> - - - - - * * - - - - - - - - * | - * | <-- DataBus5
LC21 -> - - - - - - * - - - - - - - - * | - * | <-- DataBus6
LC27 -> * * * * - - - - - - - - - - * - | - * | <-- DataInc0
LC28 -> - * * * - - - - - - - - - - * - | - * | <-- DataInc1
LC30 -> - - * * - - - - - - - - - - * - | - * | <-- DataInc2
LC31 -> - - - * - - - - - - - - - - * - | - * | <-- DataInc3
LC25 -> - - - - * * * - - - - - - - - * | - * | <-- :116
Pin
43 -> * * * * * * * - - - - - * * - - | * * | <-- Clock
34 -> - - - - - - - * - - - - - - - - | - * | <-- DataBus0
33 -> - - - - - - - - * - - - - - - - | - * | <-- DataBus1
36 -> - - - - - - - - - * - - - - - - | - * | <-- DataBus2
41 -> - - - - - - - - - - * - - - - - | - * | <-- DataBus3
2 -> - - - - - - - - - - - - - - - - | - - | <-- nLockInc
1 -> - - - - - - - - - - - - - - - - | - - | <-- nReset
LC1 -> * * * * * * * - - - - * - * - - | * * | <-- CanDMAWR
LC6 -> - - - - * * * - - - - - - - - * | - * | <-- DataInc4
LC4 -> - - - - - * * - - - - - - - - * | - * | <-- DataInc5
LC5 -> - - - - - - * - - - - - - - - * | - * | <-- DataInc6
LC8 -> - - - - - - - - - - - * * - - - | - * | <-- nDMAOE
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:f:\my production\home\usb2.0\cpld test\datagenerate.rpt
datagenerate
** EQUATIONS **
Clock : INPUT;
DMADir : INPUT;
DMAing : INPUT;
nFEmpty : INPUT;
nFFull : INPUT;
nLockInc : INPUT;
nReset : INPUT;
-- Node name is 'CanDMAWR' from file "datagenerate.tdf" line 24, column 2
-- Equation name is 'CanDMAWR', location is LC001, type is buried.
CanDMAWR = DFFE( _EQ001 $ GND, GLOBAL(!Clock), VCC, VCC, VCC);
_EQ001 = DMADir & DMAing & nFFull;
-- Node name is 'DataBus0' = 'DataBuf0' from file "datagenerate.tdf" line 21, column 9
-- Equation name is 'DataBus0', location is LC023, type is bidir.
DataBus0 = TRI(DataBuf0, CanDMAWR);
DataBuf0 = DFFE( _EQ002 $ _EQ003, _EQ004, GLOBAL( nReset), VCC, VCC);
_EQ002 = !DataBuf0 & !DataInc0 & _X001;
_X001 = EXP( DataBuf0 & DataInc0);
_EQ003 = _X001;
_X001 = EXP( DataBuf0 & DataInc0);
_EQ004 = _X002;
_X002 = EXP( CanDMAWR & Clock);
-- Node name is 'DataBus1' = 'DataBuf1' from file "datagenerate.tdf" line 21, column 9
-- Equation name is 'DataBus1', location is LC024, type is bidir.
DataBus1 = TRI(DataBuf1, CanDMAWR);
DataBuf1 = DFFE( _EQ005 $ _EQ006, _EQ007, GLOBAL( nReset), VCC, VCC);
_EQ005 = _X003 & _X004;
_X003 = EXP(!DataBuf1 & !DataInc1);
_X004 = EXP( DataBuf1 & DataInc1);
_EQ006 = DataBuf0 & DataInc0;
_EQ007 = _X002;
_X002 = EXP( CanDMAWR & Clock);
-- Node name is 'DataBus2' = 'DataBuf2' from file "datagenerate.tdf" line 21, column 9
-- Equation name is 'DataBus2', location is LC022, type is bidir.
DataBus2 = TRI(DataBuf2, CanDMAWR);
DataBuf2 = DFFE( _EQ008 $ _EQ009, _EQ010, GLOBAL( nReset), VCC, VCC);
_EQ008 = DataBuf0 & DataInc0 & _X003
# DataBuf1 & DataInc1;
_X003 = EXP(!DataBuf1 & !DataInc1);
_EQ009 = _X005 & _X006;
_X005 = EXP(!DataBuf2 & !DataInc2);
_X006 = EXP( DataBuf2 & DataInc2);
_EQ010 = _X002;
_X002 = EXP( CanDMAWR & Clock);
-- Node name is 'DataBus3' = 'DataBuf3' from file "datagenerate.tdf" line 21, column 9
-- Equation name is 'DataBus3', location is LC017, type is bidir.
DataBus3 = TRI(DataBuf3, CanDMAWR);
DataBuf3 = DFFE( _EQ011 $ _EQ012, _EQ013, GLOBAL( nReset), VCC, VCC);
_EQ011 = DataBuf0 & DataInc0 & _X003 & _X005
# DataBuf1 & DataInc1 & _X005
# DataBuf2 & DataInc2;
_X003 = EXP(!DataBuf1 & !DataInc1);
_X005 = EXP(!DataBuf2 & !DataInc2);
_EQ012 = _X007 & _X008;
_X007 = EXP(!DataBuf3 & !DataInc3);
_X008 = EXP( DataBuf3 & DataInc3);
_EQ013 = _X002;
_X002 = EXP( CanDMAWR & Clock);
-- Node name is 'DataBus4' = 'DataBuf4' from file "datagenerate.tdf" line 21, column 9
-- Equation name is 'DataBus4', location is LC018, type is bidir.
DataBus4 = TRI(DataBuf4, CanDMAWR);
DataBuf4 = DFFE( _EQ014 $ _LC025, _EQ015, GLOBAL( nReset), VCC, VCC);
_EQ014 = _X009 & _X010;
_X009 = EXP(!DataBuf4 & !DataInc4);
_X010 = EXP( DataBuf4 & DataInc4);
_EQ015 = _X002;
_X002 = EXP( CanDMAWR & Clock);
-- Node name is 'DataBus5' = 'DataBuf5' from file "datagenerate.tdf" line 21, column 9
-- Equation name is 'DataBus5', location is LC019, type is bidir.
DataBus5 = TRI(DataBuf5, CanDMAWR);
DataBuf5 = DFFE( _EQ016 $ _EQ017, _EQ018, GLOBAL( nReset), VCC, VCC);
_EQ016 = DataBuf4 & DataInc4
# _LC025 & _X009;
_X009 = EXP(!DataBuf4 & !DataInc4);
_EQ017 = _X011 & _X012;
_X011 = EXP(!DataBuf5 & !DataInc5);
_X012 = EXP( DataBuf5 & DataInc5);
_EQ018 = _X002;
_X002 = EXP( CanDMAWR & Clock);
-- Node name is 'DataBus6' = 'DataBuf6' from file "datagenerate.tdf" line 21, column 9
-- Equation name is 'DataBus6', location is LC021, type is bidir.
DataBus6 = TRI(DataBuf6, CanDMAWR);
DataBuf6 = DFFE( _EQ019 $ _EQ020, _EQ021, GLOBAL( nReset), VCC, VCC);
_EQ019 = DataBuf4 & DataInc4 & _X011
# _LC025 & _X009 & _X011
# DataBuf5 & DataInc5;
_X011 = EXP(!DataBuf5 & !DataInc5);
_X009 = EXP(!DataBuf4 & !DataInc4);
_EQ020 = _X013 & _X014;
_X013 = EXP(!DataBuf6 & !DataInc6);
_X014 = EXP( DataBuf6 & DataInc6);
_EQ021 = _X002;
_X002 = EXP( CanDMAWR & Clock);
-- Node name is 'DataBus7' = 'DataBuf7' from file "datagenerate.tdf" line 21, column 9
-- Equation name is 'DataBus7', location is LC002, type is bidir.
DataBus7 = TRI(DataBuf7, CanDMAWR);
DataBuf7 = DFFE( _EQ022 $ _LC020, _EQ023, GLOBAL( nReset), VCC, VCC);
_EQ022 = _X015 & _X016;
_X015 = EXP(!DataBuf7 & !DataInc7);
_X016 = EXP( DataBuf7 & DataInc7);
_EQ023 = _X002;
_X002 = EXP( CanDMAWR & Clock);
-- Node name is 'DataInc0' from file "datagenerate.tdf" line 23, column 9
-- Equation name is 'DataInc0', location is LC027, type is buried.
DataInc0 = DFFE( DataBus0 $ GND, GLOBAL( nLockInc), VCC, VCC, VCC);
-- Node name is 'DataInc1' from file "datagenerate.tdf" line 23, column 9
-- Equation name is 'DataInc1', location is LC028, type is buried.
DataInc1 = DFFE( DataBus1 $ GND, GLOBAL( nLockInc), VCC, VCC, VCC);
-- Node name is 'DataInc2' from file "datagenerate.tdf" line 23, column 9
-- Equation name is 'DataInc2', location is LC030, type is buried.
DataInc2 = DFFE( DataBus2 $ GND, GLOBAL( nLockInc), VCC, VCC, VCC);
-- Node name is 'DataInc3' from file "datagenerate.tdf" line 23, column 9
-- Equation name is 'DataInc3', location is LC031, type is buried.
DataInc3 = DFFE( DataBus3 $ GND, GLOBAL( nLockInc), VCC, VCC, VCC);
-- Node name is 'DataInc4' from file "datagenerate.tdf" line 23, column 9
-- Equation name is 'DataInc4', location is LC006, type is buried.
DataInc4 = DFFE( DataBus4 $ GND, GLOBAL( nLockInc), VCC, VCC, VCC);
-- Node name is 'DataInc5' from file "datagenerate.tdf" line 23, column 9
-- Equation name is 'DataInc5', location is LC004, type is buried.
DataInc5 = DFFE( DataBus5 $ GND, GLOBAL( nLockInc), VCC, VCC, VCC);
-- Node name is 'DataInc6' from file "datagenerate.tdf" line 23, column 9
-- Equation name is 'DataInc6', location is LC005, type is buried.
DataInc6 = DFFE( DataBus6 $ GND, GLOBAL( nLockInc), VCC, VCC, VCC);
-- Node name is 'DataInc7' from file "datagenerate.tdf" line 23, column 9
-- Equation name is 'DataInc7', location is LC003, type is buried.
DataInc7 = DFFE( DataBus7 $ GND, GLOBAL( nLockInc), VCC, VCC, VCC);
-- Node name is 'nDMACS'
-- Equation name is 'nDMACS', location is LC026, type is output.
nDMACS = LCELL( _EQ024 $ GND);
_EQ024 = !CanDMAWR & nDMAOE;
-- Node name is 'nDMAOE' = 'CanDMARD' from file "datagenerate.tdf" line 25, column 2
-- Equation name is 'nDMAOE', location is LC008, type is output.
nDMAOE = CanDMARD~NOT;
CanDMARD~NOT = DFFE( _EQ025 $ VCC, GLOBAL(!Clock), VCC, VCC, VCC);
_EQ025 = !DMADir & DMAing & nFEmpty;
-- Node name is 'nDMARD'
-- Equation name is 'nDMARD', location is LC032, type is output.
nDMARD = LCELL( _EQ026 $ VCC);
_EQ026 = Clock & !nDMAOE;
-- Node name is 'nDMAWR'
-- Equation name is 'nDMAWR', location is LC029, type is output.
nDMAWR = LCELL( _EQ027 $ VCC);
_EQ027 = CanDMAWR & Clock;
-- Node name is ':116' from file "datagenerate.tdf" line 39, column 26
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( _EQ028 $ _EQ029);
_EQ028 = DataBuf0 & DataInc0 & _X003 & _X005 & _X007 & _X008
# DataBuf1 & DataInc1 & _X005 & _X007 & _X008
# DataBuf2 & DataInc2 & _X007 & _X008;
_X003 = EXP(!DataBuf1 & !DataInc1);
_X005 = EXP(!DataBuf2 & !DataInc2);
_X007 = EXP(!DataBuf3 & !DataInc3);
_X008 = EXP( DataBuf3 & DataInc3);
_EQ029 = DataBuf3 & DataInc3;
-- Node name is ':147' from file "datagenerate.tdf" line 39, column 26
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( _EQ030 $ _EQ031);
_EQ030 = DataBuf4 & DataInc4 & _X011 & _X013 & _X014
# _LC025 & _X009 & _X011 & _X013 & _X014
# DataBuf5 & DataInc5 & _X013 & _X014;
_X011 = EXP(!DataBuf5 & !DataInc5);
_X013 = EXP(!DataBuf6 & !DataInc6);
_X014 = EXP( DataBuf6 & DataInc6);
_X009 = EXP(!DataBuf4 & !DataInc4);
_EQ031 = DataBuf6 & DataInc6;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X002 occurs in LABs A, B
Project Information f:\my production\home\usb2.0\cpld test\datagenerate.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
ADT PALACE Compilation = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,064K
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