📄 usb20c_sim.rpt
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-- Node name is 'DataBus4' = '|datagenerate:2|DataBuf4' from file "datagenerate.tdf" line 22, column 9
-- Equation name is 'DataBus4', type is bidir
DataBus4 = TRI(_LC043, _LC051);
_LC043 = DFFE( _EQ009 $ _LC042, nDMAWR, !_EQ010, VCC, VCC);
_EQ009 = _X005 & _X006;
_X005 = EXP(!_LC043 & !_LC116);
_X006 = EXP( _LC043 & _LC116);
_EQ010 = !Addr0 & !Addr1 & !DMAing & !nPWR;
-- Node name is 'DataBus5' = '|datagenerate:2|DataBuf5' from file "datagenerate.tdf" line 22, column 9
-- Equation name is 'DataBus5', type is bidir
DataBus5 = TRI(_LC040, _LC051);
_LC040 = DFFE( _EQ011 $ _EQ012, nDMAWR, !_EQ013, VCC, VCC);
_EQ011 = _LC043 & _LC116
# _LC042 & _X005;
_X005 = EXP(!_LC043 & !_LC116);
_EQ012 = _X007 & _X008;
_X007 = EXP(!_LC004 & !_LC040);
_X008 = EXP( _LC004 & _LC040);
_EQ013 = !Addr0 & !Addr1 & !DMAing & !nPWR;
-- Node name is 'DataBus6' = '|datagenerate:2|DataBuf6' from file "datagenerate.tdf" line 22, column 9
-- Equation name is 'DataBus6', type is bidir
DataBus6 = TRI(_LC038, _LC051);
_LC038 = DFFE( _LC048 $ GND, nDMAWR, !_EQ014, VCC, VCC);
_EQ014 = !Addr0 & !Addr1 & !DMAing & !nPWR;
-- Node name is 'DataBus7' = '|datagenerate:2|DataBuf7' from file "datagenerate.tdf" line 22, column 9
-- Equation name is 'DataBus7', type is bidir
DataBus7 = TRI(_LC037, _LC051);
_LC037 = DFFE( _EQ015 $ _LC036, nDMAWR, !_EQ016, VCC, VCC);
_EQ015 = _X009 & _X010;
_X009 = EXP(!_LC010 & !_LC037);
_X010 = EXP( _LC010 & _LC037);
_EQ016 = !Addr0 & !Addr1 & !DMAing & !nPWR;
-- Node name is 'nDMACS'
-- Equation name is 'nDMACS', location is LC059, type is output.
nDMACS = LCELL( _EQ017 $ GND);
_EQ017 = !_LC001 & !_LC003 & nDMARD & nDMAWR;
-- Node name is 'nDMAOE'
-- Equation name is 'nDMAOE', location is LC035, type is output.
nDMAOE = LCELL( _EQ018 $ GND);
_EQ018 = !_LC001 & nDMARD;
-- Node name is 'nDMARD' = '|datagenerate:2|DMARDClkD' from file "datagenerate.tdf" line 29, column 2
-- Equation name is 'nDMARD', type is output
nDMARD = _LC005~NOT;
_LC005~NOT = DFFE( _EQ019 $ VCC, Clock, VCC, !_EQ020, VCC);
_EQ019 = _LC001 & nDMARD & nFEmpty;
_EQ020 = !Addr0 & !Addr1 & !DMAing & !nPWR;
-- Node name is 'nDMAWR' = '|datagenerate:2|DMAWRClkD' from file "datagenerate.tdf" line 28, column 2
-- Equation name is 'nDMAWR', type is output
nDMAWR = _LC027~NOT;
_LC027~NOT = DFFE( _EQ021 $ VCC, Clock, VCC, !_EQ022, VCC);
_EQ021 = _LC003 & nDMAWR & nFFull;
_EQ022 = !Addr0 & !Addr1 & !DMAing & !nPWR;
-- Node name is 'nPKTEND'
-- Equation name is 'nPKTEND', location is LC064, type is output.
nPKTEND = LCELL( GND $ VCC);
-- Node name is '|datagenerate:2|CanDMARD' from file "datagenerate.tdf" line 27, column 2
-- Equation name is '_LC001', type is buried
_LC001 = DFFE( _EQ023 $ GND, !Clock, VCC, VCC, VCC);
_EQ023 = !DMADir & DMAing & nFEmpty;
-- Node name is '|datagenerate:2|CanDMAWR' from file "datagenerate.tdf" line 26, column 2
-- Equation name is '_LC003', type is buried
_LC003 = DFFE( _EQ024 $ GND, !Clock, VCC, VCC, VCC);
_EQ024 = DMADir & DMAing & nFFull;
-- Node name is '|datagenerate:2|DataBuf0~1' from file "datagenerate.tdf" line 22, column 9
-- Equation name is '_LC051', type is buried
-- synthesized logic cell
_LC051 = LCELL( _EQ025 $ VCC);
_EQ025 = !_LC003 & nDMAWR;
-- Node name is '|datagenerate:2|DataInc0' from file "datagenerate.tdf" line 24, column 9
-- Equation name is '_LC033', type is buried
_LC033 = DFFE( DataBus0 $ GND, _EQ026, VCC, VCC, VCC);
_EQ026 = _X011;
_X011 = EXP(!Addr0 & Addr1 & !DMAing & !nPWR);
-- Node name is '|datagenerate:2|DataInc1' from file "datagenerate.tdf" line 24, column 9
-- Equation name is '_LC044', type is buried
_LC044 = DFFE( DataBus1 $ GND, _EQ027, VCC, VCC, VCC);
_EQ027 = _X011;
_X011 = EXP(!Addr0 & Addr1 & !DMAing & !nPWR);
-- Node name is '|datagenerate:2|DataInc2' from file "datagenerate.tdf" line 24, column 9
-- Equation name is '_LC047', type is buried
_LC047 = DFFE( DataBus2 $ GND, _EQ028, VCC, VCC, VCC);
_EQ028 = _X011;
_X011 = EXP(!Addr0 & Addr1 & !DMAing & !nPWR);
-- Node name is '|datagenerate:2|DataInc3' from file "datagenerate.tdf" line 24, column 9
-- Equation name is '_LC034', type is buried
_LC034 = DFFE( DataBus3 $ GND, _EQ029, VCC, VCC, VCC);
_EQ029 = _X011;
_X011 = EXP(!Addr0 & Addr1 & !DMAing & !nPWR);
-- Node name is '|datagenerate:2|DataInc4' from file "datagenerate.tdf" line 24, column 9
-- Equation name is '_LC116', type is buried
_LC116 = DFFE( DataBus4 $ GND, _EQ030, VCC, VCC, VCC);
_EQ030 = _X011;
_X011 = EXP(!Addr0 & Addr1 & !DMAing & !nPWR);
-- Node name is '|datagenerate:2|DataInc5' from file "datagenerate.tdf" line 24, column 9
-- Equation name is '_LC004', type is buried
_LC004 = DFFE( DataBus5 $ GND, _EQ031, VCC, VCC, VCC);
_EQ031 = _X011;
_X011 = EXP(!Addr0 & Addr1 & !DMAing & !nPWR);
-- Node name is '|datagenerate:2|DataInc6' from file "datagenerate.tdf" line 24, column 9
-- Equation name is '_LC002', type is buried
_LC002 = DFFE( DataBus6 $ GND, _EQ032, VCC, VCC, VCC);
_EQ032 = _X011;
_X011 = EXP(!Addr0 & Addr1 & !DMAing & !nPWR);
-- Node name is '|datagenerate:2|DataInc7' from file "datagenerate.tdf" line 24, column 9
-- Equation name is '_LC010', type is buried
_LC010 = DFFE( DataBus7 $ GND, _EQ033, VCC, VCC, VCC);
_EQ033 = _X011;
_X011 = EXP(!Addr0 & Addr1 & !DMAing & !nPWR);
-- Node name is '|datagenerate:2|:118' from file "datagenerate.tdf" line 43, column 26
-- Equation name is '_LC041', type is buried
_LC041 = LCELL( _EQ034 $ _EQ035);
_EQ034 = _LC025 & _LC033 & _X001 & _X003
# _LC017 & _LC044 & _X003
# _LC046 & _LC047;
_X001 = EXP(!_LC017 & !_LC044);
_X003 = EXP(!_LC046 & !_LC047);
_EQ035 = _X012 & _X013;
_X012 = EXP(!_LC034 & !_LC045);
_X013 = EXP( _LC034 & _LC045);
-- Node name is '|datagenerate:2|:121' from file "datagenerate.tdf" line 43, column 26
-- Equation name is '_LC042', type is buried
_LC042 = LCELL( _EQ036 $ _EQ037);
_EQ036 = _LC025 & _LC033 & _X001 & _X003 & _X012 & _X013
# _LC017 & _LC044 & _X003 & _X012 & _X013
# _LC046 & _LC047 & _X012 & _X013;
_X001 = EXP(!_LC017 & !_LC044);
_X003 = EXP(!_LC046 & !_LC047);
_X012 = EXP(!_LC034 & !_LC045);
_X013 = EXP( _LC034 & _LC045);
_EQ037 = _LC034 & _LC045;
-- Node name is '|datagenerate:2|:149' from file "datagenerate.tdf" line 43, column 26
-- Equation name is '_LC048', type is buried
_LC048 = LCELL( _EQ038 $ _EQ039);
_EQ038 = _LC043 & _LC116 & _X007
# _LC042 & _X005 & _X007
# _LC004 & _LC040;
_X007 = EXP(!_LC004 & !_LC040);
_X005 = EXP(!_LC043 & !_LC116);
_EQ039 = _X014 & _X015;
_X014 = EXP(!_LC002 & !_LC038);
_X015 = EXP( _LC002 & _LC038);
-- Node name is '|datagenerate:2|:152' from file "datagenerate.tdf" line 43, column 26
-- Equation name is '_LC036', type is buried
_LC036 = LCELL( _EQ040 $ _EQ041);
_EQ040 = _LC043 & _LC116 & _X007 & _X014 & _X015
# _LC042 & _X005 & _X007 & _X014 & _X015
# _LC004 & _LC040 & _X014 & _X015;
_X007 = EXP(!_LC004 & !_LC040);
_X014 = EXP(!_LC002 & !_LC038);
_X015 = EXP( _LC002 & _LC038);
_X005 = EXP(!_LC043 & !_LC116);
_EQ041 = _LC002 & _LC038;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs B, C
-- _X011 occurs in LABs A, C, H
Project Information e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = off
Automatic Global Clear = off
Automatic Global Preset = off
Automatic Global Output Enable = off
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 10
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
ADT PALACE Compilation = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,803K
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