📄 usb20c_sim.rpt
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Device-Specific Information:e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
usb20c_sim
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 1 A DFFE t 0 0 0 4 0 3 0 |datagenerate:2|CanDMARD
(12) 3 A DFFE t 0 0 0 4 0 2 1 |datagenerate:2|CanDMAWR
(40) 51 D SOFT s t 0 0 0 0 2 0 0 |datagenerate:2|DataBuf0~1
- 33 C DFFE t 1 1 0 5 0 3 2 |datagenerate:2|DataInc0
- 44 C DFFE t 1 1 0 5 0 2 2 |datagenerate:2|DataInc1
- 47 C DFFE t 1 1 0 5 0 1 2 |datagenerate:2|DataInc2
- 34 C DFFE t 1 1 0 5 0 0 2 |datagenerate:2|DataInc3
- 116 H DFFE t 1 1 0 5 0 2 2 |datagenerate:2|DataInc4
- 4 A DFFE t 1 1 0 5 0 1 2 |datagenerate:2|DataInc5
- 2 A DFFE t 1 1 0 5 0 0 2 |datagenerate:2|DataInc6
- 10 A DFFE t 1 1 0 5 0 1 0 |datagenerate:2|DataInc7
- 41 C SOFT t 4 4 0 0 8 1 0 |datagenerate:2|:118
- 42 C SOFT t 4 4 0 0 8 2 2 |datagenerate:2|:121
(23) 48 C SOFT t 4 4 0 0 7 1 0 |datagenerate:2|:149
- 36 C SOFT t 4 4 0 0 7 1 0 |datagenerate:2|:152
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
usb20c_sim
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----------- LC1 |datagenerate:2|CanDMARD
| +--------- LC3 |datagenerate:2|CanDMAWR
| | +------- LC4 |datagenerate:2|DataInc5
| | | +----- LC2 |datagenerate:2|DataInc6
| | | | +--- LC10 |datagenerate:2|DataInc7
| | | | | +- LC5 nDMARD
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'A'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC1 -> - - - - - * | * - * * - - - - | <-- |datagenerate:2|CanDMARD
LC5 -> - - - - - * | * - * * - - - - | <-- nDMARD
Pin
36 -> - - * * * * | * * * - - - - * | <-- Addr0
37 -> - - * * * * | * * * - - - - * | <-- Addr1
1 -> * * - - - * | * * - - - - - - | <-- Clock
28 -> - - * - - - | * - - - - - - - | <-- DataBus5
29 -> - - - * - - | * - - - - - - - | <-- DataBus6
30 -> - - - - * - | * - - - - - - - | <-- DataBus7
34 -> * * - - - - | * - - - - - - - | <-- DMADir
21 -> * * * * * * | * * * - - - - * | <-- DMAing
20 -> * - - - - * | * - - - - - - - | <-- nFEmpty
18 -> - * - - - - | * * - - - - - - | <-- nFFull
9 -> - - * * * * | * * * - - - - * | <-- nPWR
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
usb20c_sim
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----- LC25 DataBus0
| +--- LC17 DataBus1
| | +- LC27 nDMAWR
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'B'
LC | | | | A B C D E F G H | Logic cells that feed LAB 'B':
LC25 -> * * - | - * * - - - - - | <-- DataBus0
LC17 -> - * - | - * * - - - - - | <-- DataBus1
LC27 -> * * * | - * * * - - - - | <-- nDMAWR
Pin
36 -> * * * | * * * - - - - * | <-- Addr0
37 -> * * * | * * * - - - - * | <-- Addr1
1 -> - - * | * * - - - - - - | <-- Clock
21 -> * * * | * * * - - - - * | <-- DMAing
18 -> - - * | * * - - - - - - | <-- nFFull
9 -> * * * | * * * - - - - * | <-- nPWR
LC3 -> - - * | - * - * - - - - | <-- |datagenerate:2|CanDMAWR
LC33 -> * * - | - * * - - - - - | <-- |datagenerate:2|DataInc0
LC44 -> - * - | - * * - - - - - | <-- |datagenerate:2|DataInc1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
usb20c_sim
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------------- LC46 DataBus2
| +--------------------------- LC45 DataBus3
| | +------------------------- LC43 DataBus4
| | | +----------------------- LC40 DataBus5
| | | | +--------------------- LC38 DataBus6
| | | | | +------------------- LC37 DataBus7
| | | | | | +----------------- LC33 |datagenerate:2|DataInc0
| | | | | | | +--------------- LC44 |datagenerate:2|DataInc1
| | | | | | | | +------------- LC47 |datagenerate:2|DataInc2
| | | | | | | | | +----------- LC34 |datagenerate:2|DataInc3
| | | | | | | | | | +--------- LC41 |datagenerate:2|:118
| | | | | | | | | | | +------- LC42 |datagenerate:2|:121
| | | | | | | | | | | | +----- LC48 |datagenerate:2|:149
| | | | | | | | | | | | | +--- LC36 |datagenerate:2|:152
| | | | | | | | | | | | | | +- LC35 nDMAOE
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
LC46 -> * - - - - - - - - - * * - - - | - - * - - - - - | <-- DataBus2
LC45 -> - - - - - - - - - - * * - - - | - - * - - - - - | <-- DataBus3
LC43 -> - - * * - - - - - - - - * * - | - - * - - - - - | <-- DataBus4
LC40 -> - - - * - - - - - - - - * * - | - - * - - - - - | <-- DataBus5
LC38 -> - - - - - - - - - - - - * * - | - - * - - - - - | <-- DataBus6
LC37 -> - - - - - * - - - - - - - - - | - - * - - - - - | <-- DataBus7
LC33 -> * - - - - - - - - - * * - - - | - * * - - - - - | <-- |datagenerate:2|DataInc0
LC44 -> * - - - - - - - - - * * - - - | - * * - - - - - | <-- |datagenerate:2|DataInc1
LC47 -> * - - - - - - - - - * * - - - | - - * - - - - - | <-- |datagenerate:2|DataInc2
LC34 -> - - - - - - - - - - * * - - - | - - * - - - - - | <-- |datagenerate:2|DataInc3
LC41 -> - * - - - - - - - - - - - - - | - - * - - - - - | <-- |datagenerate:2|:118
LC42 -> - - * * - - - - - - - - * * - | - - * - - - - - | <-- |datagenerate:2|:121
LC48 -> - - - - * - - - - - - - - - - | - - * - - - - - | <-- |datagenerate:2|:149
LC36 -> - - - - - * - - - - - - - - - | - - * - - - - - | <-- |datagenerate:2|:152
Pin
36 -> * * * * * * * * * * - - - - - | * * * - - - - * | <-- Addr0
37 -> * * * * * * * * * * - - - - - | * * * - - - - * | <-- Addr1
1 -> - - - - - - - - - - - - - - - | * * - - - - - - | <-- Clock
17 -> - - - - - - * - - - - - - - - | - - * - - - - - | <-- DataBus0
22 -> - - - - - - - * - - - - - - - | - - * - - - - - | <-- DataBus1
24 -> - - - - - - - - * - - - - - - | - - * - - - - - | <-- DataBus2
25 -> - - - - - - - - - * - - - - - | - - * - - - - - | <-- DataBus3
21 -> * * * * * * * * * * - - - - - | * * * - - - - * | <-- DMAing
9 -> * * * * * * * * * * - - - - - | * * * - - - - * | <-- nPWR
LC25 -> * - - - - - - - - - * * - - - | - * * - - - - - | <-- DataBus0
LC17 -> * - - - - - - - - - * * - - - | - * * - - - - - | <-- DataBus1
LC1 -> - - - - - - - - - - - - - - * | * - * * - - - - | <-- |datagenerate:2|CanDMARD
LC116-> - - * * - - - - - - - - * * - | - - * - - - - - | <-- |datagenerate:2|DataInc4
LC4 -> - - - * - - - - - - - - * * - | - - * - - - - - | <-- |datagenerate:2|DataInc5
LC2 -> - - - - - - - - - - - - * * - | - - * - - - - - | <-- |datagenerate:2|DataInc6
LC10 -> - - - - - * - - - - - - - - - | - - * - - - - - | <-- |datagenerate:2|DataInc7
LC5 -> - - - - - - - - - - - - - - * | * - * * - - - - | <-- nDMARD
LC27 -> * * * * * * - - - - - - - - - | - * * * - - - - | <-- nDMAWR
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
usb20c_sim
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----- LC51 |datagenerate:2|DataBuf0~1
| +--- LC59 nDMACS
| | +- LC64 nPKTEND
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'D'
LC | | | | A B C D E F G H | Logic cells that feed LAB 'D':
Pin
1 -> - - - | * * - - - - - - | <-- Clock
LC1 -> - * - | * - * * - - - - | <-- |datagenerate:2|CanDMARD
LC3 -> * * - | - * - * - - - - | <-- |datagenerate:2|CanDMAWR
LC5 -> - * - | * - * * - - - - | <-- nDMARD
LC27 -> * * - | - * * * - - - - | <-- nDMAWR
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
usb20c_sim
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+- LC116 |datagenerate:2|DataInc4
|
| Other LABs fed by signals
| that feed LAB 'H'
LC | | A B C D E F G H | Logic cells that feed LAB 'H':
Pin
36 -> * | * * * - - - - * | <-- Addr0
37 -> * | * * * - - - - * | <-- Addr1
1 -> - | * * - - - - - - | <-- Clock
27 -> * | - - - - - - - * | <-- DataBus4
21 -> * | * * * - - - - * | <-- DMAing
9 -> * | * * * - - - - * | <-- nPWR
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:e:\my production\datie\usb2.0\cpld_0403\usb20c_sim.rpt
usb20c_sim
** EQUATIONS **
Addr0 : INPUT;
Addr1 : INPUT;
Clock : INPUT;
DMADir : INPUT;
DMAing : INPUT;
nFEmpty : INPUT;
nFFull : INPUT;
nPWR : INPUT;
-- Node name is 'DataBus0' = '|datagenerate:2|DataBuf0' from file "datagenerate.tdf" line 22, column 9
-- Equation name is 'DataBus0', type is bidir
DataBus0 = TRI(_LC025, _LC051);
_LC025 = TFFE( _LC033, nDMAWR, !_EQ001, VCC, VCC);
_EQ001 = !Addr0 & !Addr1 & !DMAing & !nPWR;
-- Node name is 'DataBus1' = '|datagenerate:2|DataBuf1' from file "datagenerate.tdf" line 22, column 9
-- Equation name is 'DataBus1', type is bidir
DataBus1 = TRI(_LC017, _LC051);
_LC017 = DFFE( _EQ002 $ _EQ003, nDMAWR, !_EQ004, VCC, VCC);
_EQ002 = _X001 & _X002;
_X001 = EXP(!_LC017 & !_LC044);
_X002 = EXP( _LC017 & _LC044);
_EQ003 = _LC025 & _LC033;
_EQ004 = !Addr0 & !Addr1 & !DMAing & !nPWR;
-- Node name is 'DataBus2' = '|datagenerate:2|DataBuf2' from file "datagenerate.tdf" line 22, column 9
-- Equation name is 'DataBus2', type is bidir
DataBus2 = TRI(_LC046, _LC051);
_LC046 = DFFE( _EQ005 $ _EQ006, nDMAWR, !_EQ007, VCC, VCC);
_EQ005 = _LC025 & _LC033 & _X001
# _LC017 & _LC044;
_X001 = EXP(!_LC017 & !_LC044);
_EQ006 = _X003 & _X004;
_X003 = EXP(!_LC046 & !_LC047);
_X004 = EXP( _LC046 & _LC047);
_EQ007 = !Addr0 & !Addr1 & !DMAing & !nPWR;
-- Node name is 'DataBus3' = '|datagenerate:2|DataBuf3' from file "datagenerate.tdf" line 22, column 9
-- Equation name is 'DataBus3', type is bidir
DataBus3 = TRI(_LC045, _LC051);
_LC045 = DFFE( _LC041 $ GND, nDMAWR, !_EQ008, VCC, VCC);
_EQ008 = !Addr0 & !Addr1 & !DMAing & !nPWR;
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