fpga_states.txt

来自「一款MP3 Player Firmware 的原代码,非常有参考价值」· 文本 代码 · 共 68 行

States used by the controller in the FPGA.

Someday, this file will be more organized and might even have
descriptions of the operations these groups of signals are
intended to perform in each state.



S_RD_REG: REG_RD

S_WR_REG: REG_WR

S_RD_DRAM_1: USE_ROW, A_EN
S_RD_DRAM_2: RAS, A_EN
S_RD_DRAM_3: RAS, CAS
S_RD_DRAM_4: RAS, CAS, D16_IN_BOTH
S_RD_DRAM_5: D16_RD

S_WR_DRAM_1: USE_ROW, A_EN
S_WR_DRAM_2: RAS, A_EN
S_WR_DRAM_3: RAS, CAS
S_WR_DRAM_4: RAS, CAS, D16_IN_BOTH
S_WR_DRAM_5: RAS, D16_WR, D16_OUT_BOTH
S_WR_DRAM_6: RAS, DRAM_WE, D16_OUT_EN
S_WR_DRAM_7: RAS, DRAM_WE, CAS, D16_OUT_EN

S_RD_IDE_1:  IDE_ADDR, A_EN
S_RD_IDE_2:
S_RD_IDE_3: IDE_RD
S_RD_IDE_4: IDE_RD
S_RD_IDE_5: IDE_RD, D16_IN_BOTH
S_RD_IDE_6: D16_RD

S_WR_IDE_1: IDE_ADDR, A_EN
S_WR_IDE_2: D16_OUT_ONE, D16_OUT_EN, D16_WR
S_WR_IDE_3: IDE_WR, D16_OUT_EN
S_WR_IDE_4: IDE_WR, D16_OUT_EN
S_WR_IDE_5: IDE_WR, D16_OUT_EN
S_WR_IDE_6:


S_IDEXFER_1: IDE_ADDR_ZERO, A_EN
S_IDEXFER_2: DMA_ADDR, CA1, DEC
S_IDEXFER_3: DMA_ADDR, CA1, DEC, SHM_WR_EN, IDE_RD
S_IDEXFER_4: DMA_ADDR, CA0, INC, IDE_RD
S_IDEXFER_5: DMA_ADDR, CA0, INC, SHM_WR_EN, IDE_RD, D16_IN_BOTH
S_IDEXFER_6: DMA_ADDR, CA0, USE_ROW, A_EN, D16_OUT_BOTH
S_IDEXFER_7: DMA_ADDR, CA0, RAS, INC, A_EN
S_IDEXFER_8: DMA_ADDR, CA0, RAS, INC, SHM_WR_EN, DRAM_WE, D16_OUT_EN
S_IDEXFER_9: DMA_ADDR, CA1, RAS, DRAM_WE, CAS, D16_OUT_EN
S_IDEXFER_END:


S_STA013_0: DMA_ADDR, CA2
S_STA013_1: DMA_ADDR, CA2, USE_ROW, A_EN
S_STA013_2: DMA_ADDR, CA2, RAS, INC, A_EN
S_STA013_3: DMA_ADDR, CA2, RAS, INC, CAS, SHM_WR_EN
S_STA013_4: DMA_ADDR, CA2, RAS, INC, CAS, D16_IN_BOTH
S_STA013_5: DMA_ADDR, CA2, INC, SR_LOAD, SHM_WR_EN
S_STA013_6: DMA_ADDR, CA0, DEC, CA2
S_STA013_7: DMA_ADDR, CA0, DEC, CA2, SHM_WR_EN
S_STA013_END: