📄 inittarget.s
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;// ******************************************************************************************
;// * NAME : InitTarget.s *
;// * Version : 10.JAn.2003 *
;// * Description: *
;// * C start up codes *
;// * Configure memory, Initialize ISR ,stacks *
;// * Initialize C-variables *
;// * Fill zeros into zero-initialized C-variables *
;// ******************************************************************************************
GET ..\inc\option.s
GET ..\inc\memcfg.s
;//Interrupt Control
INTPND EQU 0x01E00004
INTMOD EQU 0x01E00008
INTMSK EQU 0x01E0000C
I_ISPR EQU 0x01E00020
I_ISPC EQU 0x1E000024
I_CMST EQU 0x01E0001C
;//Watchdog timer
WTCON EQU 0x01D30000
;//Clock Controller
PLLCON EQU 0x01d80000
CLKCON EQU 0x01d80004
LOCKTIME EQU 0x01d8000C
;//Memory Controller
REFRESH EQU 0x01C80024
;//Pre-defined constants
USERMODE EQU 0x10
SYSMODE EQU 0x1F
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1B
MODEMASK EQU 0x1F
NOINT EQU 0xC0
T_BIT EQU 0x20
BIT_TIMER0 EQU 0x01
EXPORT I_ISPC
EXPORT USERMODE
EXPORT SYSMODE
EXPORT FIQMODE
EXPORT IRQMODE
EXPORT SVCMODE
EXPORT ABORTMODE
EXPORT UNDEFMODE
EXPORT MODEMASK
EXPORT NOINT
EXPORT T_BIT
EXPORT BIT_TIMER0
EXPORT SwiFirstHandler
IMPORT SwiSecondHandler
EXPORT IsrIRQ
IMPORT OSIntNesting
IMPORT OSIntExit
IMPORT OSTickISR
IMPORT OS_TASK_SW
IMPORT OSStartHighRdy
IMPORT |Image$$RO$$Limit| ;// End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ;// Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ;// Base and limit of area
IMPORT |Image$$ZI$$Limit| ;// to zero initialise
IMPORT Main ;// The main entry of mon program
AREA Init,CODE,READONLY
ENTRY
ldr pc,Reset
ldr pc,Undefine
ldr pc,SWI
ldr pc,ProgramAbort
ldr pc,DataAbort
b .
ldr pc,IRQ
ldr pc,FIQ
Reset dcd Start
Undefine dcd 0
SWI dcd SwiFirstHandler
ProgramAbort dcd 0
DataAbort dcd 0
Reserved dcd 0
IRQ dcd IsrIRQ
FIQ dcd 0
ADC dcd 0
RTC dcd 0
UTXD1 dcd 0
UTXD0 dcd 0
SIO dcd 0
IIC dcd 0
URXD1 dcd 0
URXD0 dcd 0
TIMER5 dcd 0
TIMER4 dcd 0
TIMER3 dcd 0
TIMER2 dcd 0
TIMER1 dcd 0
TIMER0 dcd OSTickISR
UERR01 dcd 0
WDT dcd 0
BDMA1 dcd 0
BDMA0 dcd 0
ZDMA1 dcd 0
ZDMA0 dcd 0
TICK dcd 0
EINT4567 dcd 0
EINT3 dcd 0
EINT2 dcd 0
EINT1 dcd 0
EINT0 dcd 0
IsrIRQ ;//using I_ISPR register.
sub lr,lr,#4 ;//reserved for return
stmfd sp!,{r0-r3,r12,lr} ;//restore the contexts of task to interrupted
;//IMPORTANT CAUTION
;//if I_ISPC isn't used properly, I_ISPR can be 0 in this routine.
ldr r0,=OSIntNesting ;//OSIntNesting+1
ldrb r1,[r0]
add r1,r1,#1
strb r1,[r0]
ldr r1,= I_ISPR
ldr r1,[r1]
cmp r1,#0x0 ;//if the idel mode work_around is used r9 may 0 sometimes
beq %F2
mov r0,#0x0
0
movs r1,r1,lsr #1
bcs %F1
add r0,r0,#4
b %B0
1
ldr r1,=ADC
add r1,r1,r0
ldr pc,[r1] ;//call the interrupt service program
bl OSIntExit
2
ldmfd sp!,{r0-r3,r12,pc} ;//return
SwiFirstHandler
LDR SP,=SVCStack ;//it is very important
STMFD SP!,{R0-R3,R12,LR} ;// Store registers
MOV R1,SP ;//Set pointer to parameters
MRS R3,SPSR
TST R3,#T_BIT ;//Test whether thunmb state
LDRNEH R0,[LR,#-2] ;//THUMB state
BICNE R0,R0,#0xFF00
LDREQ R0,[LR,#-4] ;//ARM state
BICEQ R0,R0,#0xFF000000
;R0 contains SWI number
CMP R0,#1
LDRLO PC,=OS_TASK_SW ;//SWI number is 0
LDREQ PC,=OSStartHighRdy ;//SWI number is 1
BL SwiSecondHandler
LDMFD SP!,{R0-R3,R12,PC}^
;//******************************************************************************************
;//* START *
;//******************************************************************************************
Start
ldr r0,=WTCON ;//watch dog disable
ldr r1,=0x0
str r1,[r0]
ldr r0,=INTMSK
ldr r1,=0x07ffffff ;//all interrupt disable
str r1,[r0]
;//******************************************************************************************
;//* Set clock control registers *
;//******************************************************************************************
ldr r0,=LOCKTIME
ldr r1,=800 ;// count = t_lock * Fin (t_lock=200us, Fin=4MHz) = 800
str r1,[r0]
[ PLLONSTART
ldr r0,=PLLCON ;//temporary setting of PLL
ldr r1,=((M_DIV<<12)+(P_DIV<<4)+S_DIV) ;//Fin=10MHz,Fout=40MHz
str r1,[r0]
]
ldr r0,=CLKCON
ldr r1,=0x7ff8 ;//All unit block CLK enable
str r1,[r0]
;//******************************************************************************************
;//* Set memory control registers *
;//******************************************************************************************
ldr r0,=SMRDATA
ldmia r0,{r1-r13}
ldr r0,=0x01c80000 ;//BWSCON Address
stmia r0,{r1-r13}
;//******************************************************************************************
;//* Initialize stacks *
;//******************************************************************************************
ldr sp, =SVCStack ;//Why?
bl InitStacks
;//******************************************************************************************
;//* Copy and paste RW data/zero initialized data *
;//******************************************************************************************
LDR r0, =|Image$$RO$$Limit| ;// Get pointer to ROM data
LDR r1, =|Image$$RW$$Base| ;// and RAM copy
LDR r3, =|Image$$ZI$$Base|
;//Zero init base => top of initialised data
CMP r0, r1 ;// Check that they are different
BEQ %F1
0
CMP r1, r3 ;// Copy init data
LDRCC r2, [r0], #4 ;//--> LDRCC r2, [r0] + ADD r0, r0, #4
STRCC r2, [r1], #4 ;//--> STRCC r2, [r1] + ADD r1, r1, #4
BCC %B0
1
LDR r1, =|Image$$ZI$$Limit| ;// Top of zero init segment
MOV r2, #0
2
CMP r3, r1 ;// Zero init
STRCC r2, [r3], #4
BCC %B2
MRS R1,CPSR
ORR R1,R1,#0xFF
BIC R1,R1,#0x0F
MSR CPSR_c,R1 ;//USER mode and turn off all interrupt
BL Main ;//the initialize works of target has finished,
;//then enter apply program
;//******************************************************************************************
;//* The function for initializing stack *
;//******************************************************************************************
InitStacks
;//Don't use DRAM,such as stmfd,ldmfd......
;//SVCstack is initialized before
;//Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;//UndefMode
ldr sp,=UndefStack
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;//AbortMode
ldr sp,=AbortStack
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;//IRQMode
ldr sp,=IRQStack
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;//FIQMode
ldr sp,=FIQStack
orr r1,r0,#SYSMODE|NOINT
msr cpsr_cxsf,r1 ;//SYSMode or USERMode
ldr sp,=UserStack
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;//SVCMode
ldr sp,=SVCStack
;//USER mode is not initialized.
mov pc,lr ;//The LR register may be not valid for the mode changes.
;//******************************************************************************************
;//* The function for entering power down mode *
;//******************************************************************************************
;//void EnterPWDN(int CLKCON);
EnterPWDN
mov r2,r0 ;//r0=CLKCON
ldr r0,=REFRESH
ldr r3,[r0]
mov r1, r3
orr r1, r1, #0x400000 ;//self-refresh enable
str r1, [r0]
nop ;//Wait until self-refresh is issued. May not be needed.
nop ;//If the other bus master holds the bus, ...
nop ;// mov r0, r0
nop
nop
nop
nop
;//enter POWERDN mode
ldr r0,=CLKCON
str r2,[r0]
;//wait until enter SL_IDLE,STOP mode and until wake-up
mov r0,#0xff
0 subs r0,r0,#1
bne %B0
;//exit from DRAM/SDRAM self refresh mode.
ldr r0,=REFRESH
str r3,[r0]
mov pc,lr
LTORG
SMRDATA DATA
;//******************************************************************************************
;//* Memory configuration has to be optimized for best performance *
;//* The following parameter is not optimized. *
;//******************************************************************************************
;//*** memory access cycle parameter strategy ***
;// 1) Even FP-DRAM, EDO setting has more late fetch point by half-clock
;// 2) The memory settings,here, are made the safe parameters even at 66Mhz.
;// 3) FP-DRAM Parameters:tRCD=3 for tRAC, tcas=2 for pad delay, tcp=2 for bus load.
;// 4) DRAM refresh rate is for 40Mhz.
DCD 0x11110090 ;Bank0=OM[1:0], Bank1~Bank7=16bit, bank2=8bit;
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;//GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;//GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;//GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;//GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;//GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;//GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;//GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;//GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;//REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
DCD 0x16 ;//SCLK power mode, BANKSIZE 32M/32M
DCD 0x20 ;//MRSR6 CL=2clk
DCD 0x20 ;//MRSR7
ALIGN
AREA RamData, DATA, READWRITE
^ (_ISR_STARTADDRESS-0x500)
UserStack # 256 ;c1(c7)ffa00
SVCStack # 256 ;c1(c7)ffb00
UndefStack # 256 ;c1(c7)ffc00
AbortStack # 256 ;c1(c7)ffd00
IRQStack # 256 ;c1(c7)ffe00
FIQStack # 0 ;c1(c7)fff00
END
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