flashi_nand_ctlr_a.h

Flash的驱动程序。包括市面上常见的Nor Flash和Nand Flash.基本上所有的Flash只需要简单修改就可以移植到其他应用。

#ifndef __FLASHI_NAND_CTLR_A_H__
#define __FLASHI_NAND_CTLR_A_H__

/**********************************************************************
 * flashi_nand_ctlr_a.h
 *
 * Nand Device interface.
 *
 * This header file includes all the function interfaces internal to NAND Controller A
 * used by - MSMs 6280
 *
 * Copyright (C) 2004-2006 Qualcomm, Inc.  All Rights Reserved.
 *
 **********************************************************************/


/*===========================================================================

                        EDIT HISTORY FOR MODULE

  This section contains comments describing changes made to the module.
  Notice that changes are listed in reverse chronological order.

  $Header: //depot/asic/msmshared/drivers/flash/MSM_FLASH.01.04/flashi_nand_ctlr_a.h#1 $ $DateTime: 2006/05/16 22:40:13 $ $Author: dhamimp $

when         who     what, where, why
--------     ---     ----------------------------------------------------------
2006-05-04   dp      Adding controller abstraction layer
2006-02-17   rt      Add functions to clear OP and WR_ERR INT bits individually
2005-08-02   drh     Changes to compile in L4 environment
2005-04-28   drh     Add function prototype
2004-09-30   drh     Move partition functions out to partition specific file
2004-09-29   drh     Remove extern no longer needed
2004-09-22   rg      added check for rex_is_initialized() for locks
2004-08-09   drh     Added support for ECC manipulation
2004-07-20    gr     Added multi-threading support.
2004-07-20   drh     Do not compile partition functions for boot_loader
2004-03-08   dlb     Rename FS_NAND... to FLASH_NAND...
2004-03-31   drh     Move NAND controller specific defines to flash_nand_msm.h 
                     in preparation for new controller type modifications.
2004-03-30   drh     Add external function prototype
2004-03-19   drh     Integrate functionality to ask if NAND controller is busy.
                     Change partition manipulation function prototypes.
2004-02-23   drh     Move MSM specific defines to fs_nand_msm.h.
                     Add new externs for private data returning functions.
2004-01-21   drh     Came from services/efs/flash_nand_device.h


===========================================================================*/

#include "flash.h"
#include "flashi.h"
#ifndef FS_UNIT_TEST
  #include "msm.h"
#endif
#include "flash_nand_msm.h"

/* Log to the base 2 of number of bytes in a Code Word */
#define FLASH_NAND_PAGE_ADDR_BITS      9

#define FLASH_NAND_UD_PER_CW           512  /* User Data per CW */
#define FLASH_NAND_SA_PER_CW           16   /* Spare Area per CW */

#define FLASH_NAND_CW_CNT_512          (FLASH_NAND_PAGE_SIZE_512 /      \
                                        FLASH_NAND_UD_PER_CW)
#define FLASH_NAND_CW_CNT_2048         (FLASH_NAND_PAGE_SIZE_2048 /     \
                                        FLASH_NAND_UD_PER_CW)


/* General Nand Controller Related Definitions */
#define FLASH_NAND_SFT_RESET_CMD       0x0
#define FLASH_NAND_PAGE_READ_CMD       0x1
#define FLASH_NAND_FLAG_READ_CMD       0x2
#define FLASH_NAND_PAGE_WRITE_CMD      0x3
#define FLASH_NAND_BLOCK_ERASE_CMD     0x4
#define FLASH_NAND_ID_FETCH_CMD        0x5
#define FLASH_NAND_STATUS_CMD          0x6 
#define FLASH_NAND_RESET_FLSH_MEM_CMD  0x7

/* 
 * ECC error masks. These correspond to bit positions in the ECC_0_RW,
 * ECC_1_RW, ECC_2_RW and ECC_3_RW registers. Note that ECC_READ_ERR
 * - bit 29 - is a correctable error (automatically corrected by the ECC).
 */

#define FLASH_NAND_ECC_UNCORRECTABLE_ERR_MASK 0x80000000    /* Bit 31 */
#define FLASH_NAND_ECC_ERR_MASK               (FLASH_NAND_ECC_UNCORRECTABLE_ERR_MASK)
  
/* Bit definitions for NAND config register */
#define FLASH_NAND_CFG1_ERR_DET_ON          0x0000

/* Bit definitions for NAND config register */
#define FLASH_NAND_CFG1_BUS_FREE_LOW        0x0000
#define FLASH_NAND_CFG1_BUS_FREE_NO_LOW     0x0002

#define FLASH_NAND_CFG1_ECC_ENABLE          0x0000
#define FLASH_NAND_CFG1_ECC_DISABLE         0x0001

#define FLASH_NAND_CFG1_16BIT_NAND          0x0080
#define FLASH_NAND_CFG1_8BIT_NAND           0x0000

/* Note that the device sizes are in MB. MB size is used because 
 * they use registers more efficiently without a risk of overflow. 
 */
#define FLASH_NAND_DEV_SIZE_256MBIT         0x020  /*  32 MB = 256 Mbit */
#define FLASH_NAND_DEV_SIZE_512MBIT         0x040  /*  64 MB = 512 Mbit */
#define FLASH_NAND_DEV_SIZE_1GBIT           0x080  /* 128 MB =   1 Gbit */
#define FLASH_NAND_DEV_SIZE_2GBIT           0x100  /* 256 MB =   2 Gbit */

/* NAND device size related drfinitions for CFG1 register */
#define FLASH_NAND_CFG1_SIZE_256MBIT        0x0001 /* b0001 */
#define FLASH_NAND_CFG1_SIZE_512MBIT        0x0002 /* b0010 */
#define FLASH_NAND_CFG1_SIZE_1GBIT          0x0004 /* b0100 */
#define FLASH_NAND_CFG1_SIZE_2GBIT          0x0008 /* b1000 */

#define NAND_OPT_ON                         0x1      /* Turn on an option */
#define NAND_OPT_OFF                        0x0      /* Turn off an option */

#define FLASH_NAND_STATUS_ECC_ANY_ERR_MASK   (FLASH_NAND_ECC_ERR_MASK)

#define FLASH_NAND_STATUS_READ_ANY_ERR_MASK                                    \
                                      (FLASH_NAND_ECC_ERR_MASK |               \
                                       HWIO_NAND_FLASH_STATUS_OP_ERR_BMSK)

#define FLASH_NAND_STATUS_WR_ER_ANY_ERR_MASK                                   \
                                      (HWIO_NAND_FLASH_STATUS_OP_RESULT_BMSK | \
                                       HWIO_NAND_FLASH_STATUS_OP_ERR_BMSK)

#define FLASH_NAND_STATUS_OP_ERR_MASK (HWIO_NAND_FLASH_STATUS_OP_ERR_BMSK)

/* Clear interrupt indication before issuing command*/
#define FLASH_NAND_FLASH_CMD(priv, x)      do {                                \
                                           priv->ctlr.clear_op_status_bit ();  \
                                           HWIO_OUT(NAND_FLASH_CMD, x);        \
                                           } while (0)
           
#define FLASH_NAND_FLASH_STATUS()          HWIO_IN(NAND_FLASH_STATUS)

#define FLASH_NAND_FLASH_ADDR(x)           HWIO_OUT(NAND_FLASH_ADDR, x)

#define FLASH_NAND_SPARE_UNIT()            HWIO_IN(NAND_SPARE_BYTE);

/* NOTE:
 *  We do not manipulate the ECC bit in both the real register and the
 *  shadow copy because we always call the ENABLE or DISABLE ECC
 *  macro after copying the shadow value to the real register.  So, we
 * only need to manipulate the real register, since it is readable.
 */
#define FLASH_NAND_ENABLE_ECC()           HWIO_OUTM(NAND_FLASH_CFG1,      \
                                          HWIO_FMSK(NAND_FLASH_CFG1, ECC_DISABLE), 0x0)

#define FLASH_NAND_DISABLE_ECC()          HWIO_OUTM(NAND_FLASH_CFG1, \
                                          HWIO_FMSK(NAND_FLASH_CFG1, ECC_DISABLE), 0x1)

/* write whatever the shadow kept */
#define FLASH_NAND_WRITE_CFG_SHADOW(priv)                           \
  do {                                                              \
    HWIO_OUT(NAND_FLASH_CFG1, priv->NAND_CFG1);                     \
    HWIO_OUT(NAND_FLASH_CFG2, priv->NAND_CFG2);                     \
    HWIO_OUT(NAND_FLASH_COMMON_CFG, priv->NAND_COMMON_CFG);         \
  } while (0)

/* BAD block offsets are based on 1-based count in 1st Code Word */

/* Bad block marker offsets for 512 byte NAND devices */
#define FLASH_NAND_8BIT_BAD_BLOCK_FLAG_OFFSET       5  /* 517th byte */
#define FLASH_NAND_16BIT_BAD_BLOCK_FLAG_OFFSET      0  /* 256th word */

/* Bad block flag offsets (in first CW) for 2K byte NAND devices */
#define FLASH_NAND_2K_8BIT_BAD_BLOCK_FLAG_OFFSET    0  /* 512th byte */ 
#define FLASH_NAND_2K_16BIT_BAD_BLOCK_FLAG_OFFSET   0  /* 256th word */

/* Macros to indicate busy/idle state of NAND device */
#define FLASH_NAND_SET_BUSY() flash_nand_ctlr_a_busy = TRUE
#define FLASH_NAND_SET_IDLE() flash_nand_ctlr_a_busy = FALSE

/* 
 * Controller specific flags for NAND controller 
 */

/* Codeword count for the device we are dealing with */
#define NAND_CW_COUNT          ctlr.ctlr_specific_flags[0]

/* Locations for saving config values set by PBL from config data for 
 * NAND controller A.
 * Needed because a NAND controller reset will destroy the values
 * and we need to restore them after the reset.
 */
#define NAND_COMMON_CFG        ctlr.ctlr_specific_flags[1]
#define NAND_CFG1              ctlr.ctlr_specific_flags[2]
#define NAND_CFG2              ctlr.ctlr_specific_flags[3]

/* Current state of ECC - Enabled/Disabled */
#define NAND_ECC_STATE         ctlr.ctlr_specific_flags[4]

/****************************************************************
 * Global Data Prototypes
 ***************************************************************/
/* Prototypes and macros related to multithreading support.
 */

#ifdef FEATURE_IG_EFS_EXT_SERVER
  #ifndef FLASH_NAND_SINGLE_THREADED
    #define FLASH_NAND_SINGLE_THREADED
  #endif
#endif

#ifndef FLASH_NAND_SINGLE_THREADED

#include "rex.h" 

#define FLASH_NAND_INIT_LOCK()\
  do {\
    if (rex_is_initialized ()) {\
      INTLOCK();\
      if (!flash_nand_ctlr_a_lock_initialized) {\
        rex_init_crit_sect (&flash_nand_ctlr_a_cs);\
        flash_nand_ctlr_a_lock_initialized = 1;\
      }\
      INTFREE();\
    }\
  } while (0)

#define FLASH_NAND_LOCK()\
  do {\
    if (flash_nand_ctlr_a_lock_initialized)\
      rex_enter_crit_sect (&flash_nand_ctlr_a_cs);\
  } while (0)

#define FLASH_NAND_UNLOCK()\
  do {\
    if (flash_nand_ctlr_a_lock_initialized)\
      rex_leave_crit_sect (&flash_nand_ctlr_a_cs);\
  } while (0)

#else

#define FLASH_NAND_INIT_LOCK()
#define FLASH_NAND_LOCK()
#define FLASH_NAND_UNLOCK()

#endif /* !FLASH_NAND_SINGLE_THREADED */

/****************************************************************
 * Global Function Prototypes
 ***************************************************************/

/* Probe the devices to determine the device type */

/* Probe a particular flash device (i.e. 0, 1, 2...max devices).
 *     Caller allocates an empty fs_device_data structure and
 *     this function call fills it in if successful.  Initial values
 *     filled in allow access to entire flash and may be used
 *     immediately if the scope of the caller needs to access entire
 *     device.
 */
int flash_nand_ctlr_a_device_probe (struct fsi_device_data *self, int whichflash);

/* Returns idle/busy state of NAND controller A */
int flash_nand_ctlr_a_is_busy (void);

/****************************************************************
 * Function Prototypes
 ***************************************************************/

/* Function to wait for RESET operation to complete */
static uint32 flash_nand_ctlr_a_wait_for_rst_complete( void );

/* Function to wait for other operations to complete */
static void flash_nand_ctlr_a_wait_for_op_complete(void);

/* Function to clear OP bit in NAND interrupt register */
static void  flash_nand_ctlr_a_clear_op_status_bit(void);

/* Function to clear ER_ERR bit in NAND interrupt register */
static void  flash_nand_ctlr_a_clear_wr_err_status_bit(void);

/* Write operations. */
static int flash_nand_ctlr_a_write_page (fs_device_t self, page_id page, void *data);

/* A full block erase */
static int flash_nand_ctlr_a_erase_block (fs_device_t self, block_id block);

/* Read the data into a buffer */
static int flash_nand_ctlr_a_read_page (fs_device_t self, page_id page, void *data);

/* Determine if block is erased or not */
static int flash_nand_ctlr_a_is_block_erased (fs_device_t self, block_id block);

/* Determine if page is erased or not */
static int flash_nand_ctlr_a_is_page_erased (fs_device_t self, page_id page);

/* Clear the spare byte of the given page. */
static int flash_nand_ctlr_a_mark_block_bad (fs_device_t self, block_id block);

/* Read len bytes from spare area starting from spare_offset of given page */
static int flash_nand_ctlr_a_read_spare_bytes (fs_device_t self, page_id page, 
  uint32 spare_offset, uint32 len, void *data);

/* ID the NAND device to get its maker and device ids */
static void flash_nand_ctlr_a_id_data (fsi_device_t priv, int *maker_id, 
  int *device_id);

/* Set the ECC state variable for NAND controller */
static void flash_nand_ctlr_a_set_ecc_state (fs_device_t self, int state);

/* Set up the wait states and config values into NAND config registers */
static int flash_nand_ctlr_a_set_cfg_registers(fs_device_t self, int width, 
  uint32 page_size, uint32 device_size);

/* Determine the offset of bad block flag, in the Code Word correctly based on 
   flash width and page_size */
static int flash_nand_ctlr_a_get_bb_offset(fs_device_t self);

/* Read multiple pages by looping through all the pages one by one */
static int flash_nand_ctlr_a_read_mpages (fs_device_t self, page_id start_page, 
  page_id num_pages, void *data, void (*wdog_kick_fn_ptr)(void));

/* Copy src_page to dest_page by reading src_page into user memory */
static int flash_nand_ctlr_a_copy_page (fs_device_t self, page_id src_page, 
  page_id dest_page);

#endif /* End of __FLASHI_NAND_CTLR_A_H__ */