📄 tw101reg.h
字号:
//---------------------------------------------------------------------------
// Terawins Inc. Company Confidential Strictly Private
//
// $Archive: TW101Reg.h $
// $Revision: 1.01 $
// $Author: Bruce Cho $
// $Date: 2004/12/28 17:14:23 $
//
// --------------------------------------------------------------------------
#ifndef __TW101_REGS_H__
#include "system.h"
#define __TW101_REGS_H__
#define P1_OFFSET 0x02
#define P2_OFFSET 0x04
#define TW101_P0 0x50
#define TW101_P1 TW101_P0 + P1_OFFSET
#define TW101_P2 TW101_P0 + P2_OFFSET
#ifndef TW101
#define TW101 TW101_P0 // for compatibility
#endif
//#define TW702_WR_ADDR 0xd0
#define IF_NDEFAULT(eval_reg) ((eval_reg)!=(eval_reg##_DEFAULT))
//---------------------------------------------------------------------------
// The postfix of _REG defines its register address
// The postfix of _DEFAULT defines the default value of the register of the chip,
// and these values should not be modified
//---------------------------------------------------------------------------
/* ADC Regs */
// define the ADC R/G/B current regiser [3:0]
#define ADC_R_CUR_REG 0x00
#define ADC_R_CUR_DEFAULT 0x00
#define ADC_G_CUR_REG 0x01
#define ADC_G_CUR_DEFAULT 0x00
#define ADC_B_CUR_REG 0x02
#define ADC_B_CUR_DEFAULT 0x00
#define ADC_R_CUR 0x00
#define ADC_G_CUR 0x00
#define ADC_B_CUR 0x00
// define the ADC clamping pulse placement and duration
// [7:5] clamping pulse placement
// [4:0] clamping pulse duration
#define ADC_CLP_PPD_REG 0x04
#define ADC_CLP_PPD_DEFAULT 0x00
#define ADC_CLP_PPD 0x00
// define the ADC R/G/B static gain
// [7:0]
// Note: ADC analog AGC selection (0x1A) should be enabled
#define ADC_R_SGAIN_REG 0x07
#define ADC_R_SGAIN_DEFAULT 0x00
#define ADC_G_SGAIN_REG 0x08
#define ADC_G_SGAIN_DEFAULT 0x00
#define ADC_B_SGAIN_REG 0x09
#define ADC_B_SGAIN_DEFAULT 0x00
#ifdef T100
#define ADC_R_SGAIN 0x60
#define ADC_G_SGAIN 0x60
#define ADC_B_SGAIN 0x60
#else
#define ADC_R_SGAIN 0x80
#define ADC_G_SGAIN 0x80
#define ADC_B_SGAIN 0x80
#endif
// define the ADC R/G/B offset
// [7:2]
#define ADC_R_OFFSET_REG 0x0A
#define ADC_R_OFFSET_DEFAULT 0x80
#define ADC_R_OFFSET 0x30
#define ADC_G_OFFSET_REG 0x0B
#define ADC_G_OFFSET_DEFAULT 0x80
#define ADC_G_OFFSET 0x30
#define ADC_B_OFFSET_REG 0x0C
#define ADC_B_OFFSET_DEFAULT 0x80
#define ADC_B_OFFSET 0x30
// define the ADC general control configuration register (R/W)
// [7:6] clamping mode 0: fixed window
// 1: locked window
// 2: self bias (default)
// 3: fixed window
// [5] DC clamping enable
// [4] Clamping source selection
// [3] Slicer threshold voltage selection 0: abouve auto bias (default)
// 1: below auto bias
// [2] DC calibration ready
// [1] DC calibration enable
// [0] DC calibration mode 0: minimum (default)
// 1: average
#define ADC_GENCTRL_REG 0x0D
#define ADC_GENCTRL_DEFAULT 0x20
#define ADC_GENCTRL 0x20
// define YPbPr clamping control register (R/W)
// [7:3] reserved
// [2][1][0] B/G/R clamping mode 0: clmap to ground
// 1: clamp to midscale
#define YPbPr_CLPCTRL_REG 0x11
#define YPbPr_CLPCTRL_DEFAULT 0x00
#define YPbPr_CLPCTRL 0x05
// define analog source MUX selection (R/W)
// [7:6] reserved
// [5:4][3:2][1:0] selection for ADC channel 2/1/0, 0: ACB1/AY1/ACR1
// 1: ACB0/AY0/ACR0
// 2: ACB2/AY2/ACR2
// 3: ACB2/AY2/ACR2
#define ASRC_MUX_REG 0x18
#define ASRC_MUX_DEFAULT 0x00
#define ASRC_MUX 0x20
// define Y/Cb/Cr data switching control
// [7:6] reserved
// [5:4][3:2][1:0] selection for Cb(chroma)/Y(com)/Cr(chroma) from
// 0: ADC Ch0
// 1: ADC Ch1
// 2: ADC Ch2
// 3: ADC Ch2
#define YCbCr_SW_REG 0x19
#define YCbCr_SW_DEFAULT 0x00
#define YCbCr_SW 0x08
// define ADC analog AGC selection (R/W)
// [7:6] gain modulator 0: Positive gain
// 1: Positive gain 1x~2x
// 2: Negative gain 1x~2x
// 3: Negative gain
// [5:3] Reserved
// [2][1][0] Cb/Y/Cr gain mode 0: Statice gain (refer to 0x07~0x09)
// 1: Dynamic gain
#define ADC_AGC_SEL_REG 0x1A
#define ADC_AGC_SEL_DEFAULT 0x42
#ifdef T100
#define ADC_AGC_SEL 0x87
#else
#define ADC_AGC_SEL 0xC7
#endif
// Blank sync level (R/W), 0x1C
// [7:0] blank sync level
#define BLANK_SYNCLV_REG 0X1C
#define BLANK_SYNCLV_DEFAULT 0xC0
#define BLANK_SYNCLV 0xB8
// De-Interlaced process & vertical shadow control register (R/W),0x30
// [7] 1: enable CbCr interpolation, 0: disable
// [6] reserved
// [5] VST_CHGSEL(?)
// [4] Interrupt polarity 1: positive
// 0: negative
// [3] capture size for scaler 1: Hsize and Vsize are assigned by 0x54~0x57
// 0: size assigned by input sources
// [2] ENQKHS, set 0 for normal operation
// [1] 1: interlaced video
// 0: non-interlaced video
#define DITLC_VSHDW_REG 0x30
#define DITLC_VSHDW_DEFAULT 0x82
#define DITLC_VSHDW 0x82
// lower 8-bit HSYNC missing counter register (R/W), 0x38
// [7:0]
#define HSYNC_MISSCNT_L_REG 0x38
#define HSYNC_MISSCNT_L_DEFAULT 0x00
#define HSYNC_MISSCNT_L 0x50
// upper 8-bit HSYNC missing counter register (R/W), 0x39
// [7:0]
#define HSYNC_MISSCNT_H_REG 0x39
#define HSYNC_MISSCNT_H_DEFAULT 0x10
#define HSYNC_MISSCNT_H 0x00
// VSYNC delta difference result register (R/W), 0x3A
// [7:0]
#define VSYNC_DLT_REG 0x3A
#define VSYNC_DLT_DEFAULT 0x00
#define VSYNC_DLT 0x20
// HSYNC delta difference result register (R/W), 0x3B
// [7:0]
#define HSYNC_DLT_REG 0x3B
#define HSYNC_DLT_DEFAULT 0x00
#define HSYNC_DLT 0x03
// Left border croping, 0x40
// [7:6] reserved
// [5:0] remove pixels on left border
#define LBORDER_CROP_REG 0x40
#define LBORDER_CROP_DEFAULT 0x00
#define LBORDER_CROP 0x18
// VSYNC timing measurement register. 0x50
// [7] reserved
// [6] register 0x5C/0x5D can be HS pulse width or hsync period
// 0: period in # of pixel clock
// 1: hsync pulse width in # of pixel clock
// [5] (R)when [4]=1, a whole frame time can be obtained through XCLK counting
// see register 0x51~0x53
// after this bit read back as 1, then clear [4] first before reading 0x51~0x53
// [4] when input Vsync changes, enable this bit to start measurement on Vsync using XCLK
// [3:0] reserved
#define VSYNC_TIME_MEA_REG 0x50
#define VSYNC_TIME_MEA_DEFAULT 0x00
#define VSYNC_TIME_MEA 0x06
// Bandwidth of Digital Color Transient Improvement, 0x60
// [7:1] reserved
// [0] 0: high bandwidth
// 1: low bandwidth
#define DCTI_BW_REG 0x60
#define DCTI_BW_DEFAULT 0x00
#ifdef T100
#define DCTI_BW 0x01
#else
#define DCTI_BW 0x00
#endif
// Luma Peaking control, also refer to P2_80h, 0x61
// [7] peaking EN
// [6] reserved
// [5:0] peaking Co
#define LUMA_PKCTRL_REG 0x61
#define LUMA_PKCTRL_DEFAULT 0x08
#define LUMA_PKCTRL 0x8F
// Bandpass peaking coef, 0x62
// [7:5] reserved
// [4:0] bandpass coefficient
#define BP_PKCOEF_REG 0x62
#define BP_PKCOEF_DEFAULT 0x04
#define BP_PKCOEF 0x0F
// Highpass peaking coef, 0x63
// [7:5] reserved
// [4:0] highpass coefficient
#define HP_PKCOEF_REG 0x63
#define HP_PKCOEF_DEFAULT 0x04
#define HP_PKCOEF 0x0F
// Lowpass peaking coef, 0x64
// [7:5] reserved
// [4:0] lowpass coefficient
#define LP_PKCOEF_REG 0x64
#define LP_PKCOEF_DEFAULT 0x02
#define LP_PKCOEF 0x04
// Gain and coring of DLTI, 0x65
// [7:5] gain
// [4:0] coring
#define DLTI_GAINCO_REG 0x65
#define DLTI_GAINCO_DEFAULT 0x08
#define DLTI_GAINCO 0x08
// Gain and coring of DCTI, 0x66
// [7:5] gain
// [4:0] coring
#define DCTI_GAINCO_REG 0x66
#define DCTI_GAINCO_DEFAULT 0x08
#define DCTI_GAINCO 0x88
//Constrast adjust (on output side, for user), 0x68
// [7:0] constrast level
#define OP_CONST_REG 0x68
#define OP_CONST_DEFAULT 0x80
//Brightness adjust (on output side, for user), 0x69
// [7:0] Brightness level
#define OP_BRIGHT_REG 0x69
#define OP_BRIGHT_DEFAULT 0x80
//Hue sin adjust , 0x6A
// [7] sign bit
// [6:0] Hue sin value, ( represent -1~1)
#define OP_HUESIN_REG 0x6A
#define OP_HUESIN_DEFAULT 0x00
//Hue cos adjust , 0x6B
// [7] sign bit
// [6:0] Hue cos value, ( represent -1~1)
#define OP_HUECOS_REG 0x6B
#define OP_HUECOS_DEFAULT 0x7F
//Chroma saturation adjust (on output side, for user), 0x6C
// [7:0] constrast level
#define OP_SAT_REG 0x6C
#define OP_SAT_DEFAULT 0x80
#define OP_CONST 0x80
#define OP_BRIGHT 0x80
#define OP_SAT 0x80
#define OP_HUESIN 0x00
#define OP_HUECOS 0x7F
// Scaling general control register, 0x70
// [7:6]
// [5] reverse input odd field control for intrafield scaling,
// only take action when ITLCPRO(P0_30[1]) set to 1
// [4] software need to turn this bit on when the freq of i/p clock is higher than o/p pixel clock
// [3] remove 2D scaling for 2 pixels width chess board boundary effect
// [2] enable 2D scaler
// [1:0] reset coef table 01b: reset write pointer to 0x00
// 10b: reset write pointer to 0x80
#define SCALE_GENCTRL_REG 0x70
#define SCALE_GENCTRL_DEFAULT 0x40
#define SCALE_GENCTRL 0x90
// scaling coefficient data port register, 0x71
#define SCALE_COEFDATA_REG 0x71
// Horizontal/Vertical scale step LSB/MSB register, 0x72~0x75
// value= (output size/input size) * 2^15
// 0~0x8000 scale up, 0x8001~0xFFFF scale down
// MUST WRITE 0x75 TO MAKE IT WORK
#define HSCALE_STP_L_REG 0x72
#define HSCALE_STP_H_REG 0x73
#define VSCALE_STP_L_REG 0x74
#define VSCALE_STP_H_REG 0x75
#define HSCALE_STP_L 0xE0 // 0x33 for T100 demo
#define HSCALE_STP_H 0xB7 //0x73 for T100 demo
#define VSCALE_STP_L 0x00 //
#define VSCALE_STP_H 0x84 //0x40 for T100 demo
#define USE_PRESET_SCALE 1
// Horizontal aspect ratio register, 0x76, 0x77
// [7:0] LSB
// [7] enable aspect ratio 1: enable, 0: disable
// [6] 1: enlarge, 0: compact (center area)
// [5:0] MSB
#define HASPR_L_REG 0x76
#define HASPR_H_REG 0x77
// Line buffer configuration LSB/MSB register, 0x84, 0x85
// [7:0]
// [15:8]
// this register can cause a time delay in XCLK count between the
// leading edge of input Vsync and leading edge of output Vsync
#define LINE_BUF_L_REG 0x84
#define LINE_BUF_H_REG 0x85
#define LINE_BUF_L 0x30
#define LINE_BUF_H 0x15
#define USE_PRESET_LINE_BUF 1
// Image function control register, 0x90
// [7:6] Gamma table select 11: Gamma table R
// 10: Gamma table G
// 01: Gamma table B
// 00: All 3
// [5:3] reserved
// [2] enable CSC(color space conversion), 1: enable (default)
// [1] enable Gamma
// [0] enable Dithering
#define IMG_FUNCTRL_REG 0x90
#define IMG_FUNCTRL_DEFAULT 0x04
#ifdef T100
#define IMG_FUNCTRL 0x04
#else
#define IMG_FUNCTRL 0x05 //enable dithering
#endif
// Built-in pattern generator control register
// [7] enable frame backgroud color, refer of 0x9D~0x9F
// [6] enable pattern generator shows 9 patterns sequentially
// [7:6] 00: normal color
// 01: normal color
// 10: still pattern
// 11: motion patterns
// [5] 1: indicate 8-bit patterns
// 0: indicate 6-bit patterns
// [4] reserved
// [3:0]
#define BTIN_PATTERN_REG 0x91
#define BTIN_PATTERN_DEFAULT 0x04
#define BTIN_PATTERN 0x04
// define CSC Y coef (R/W), 0x97
// [7:0] 1.7-bit fixed point ( int*2^7 + frac*2^7)
#define CSC_YCOEF_REG 0x97
#define CSC_YCOEF_DEFAULT 0x95 //=1.164
#define CSC_YCOEF 0x95 //=1.164
// define CSC Red coef of Cr (R/W)
// [7:0] 1.7-bit fixed point ( int*2^7 + frac*2^7)
#define CSC_CrRCOEF_REG 0x98
#define CSC_CrRCOEF_DEFAULT 0xA6 //=1.297?
#define CSC_CrRCOEF 0xCC //=1.594
// define CSC Green coef of Cb (R/W)
// [7:0] 0.8-bit fixed point (frac * 2^8)
#define CSC_CbGCOEF_REG 0x99
#define CSC_CbGCOEF_DEFAULT 0x64 //=0.390
#define CSC_CbGCOEF 0x64
// define CSC Green coef of Cr (R/W)
// [7:0] 0.8-bit fixed point (frac * 2^8)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -