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📄 main.lss

📁 AVRGCC编写的很好用的串口通讯源程序
💻 LSS
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 2f2:	01 c0       	rjmp	.+2      	; 0x2f6
		}
	}
	else
	{
		UDR = c;
 2f4:	cc b9       	out	0x0c, r28	; 12
	}
	EndCritical();
 2f6:	78 94       	sei
	
	return 0;
}
 2f8:	80 e0       	ldi	r24, 0x00	; 0
 2fa:	90 e0       	ldi	r25, 0x00	; 0
 2fc:	cf 91       	pop	r28
 2fe:	08 95       	ret

00000300 <UartIOCtl>:

void
UartInit(void)
{
	uint32_t uart_param;
	
	AvrXResetSemaphore(&rx_rdy);
	AvrXResetSemaphore(&tx_rdy);
	
	uart_param = UART_DEFAULT_DATABITS;
	UartIOCtl(UART_SETDATABITS, &uart_param);
	uart_param = UART_DEFAULT_PARITY;
	UartIOCtl(UART_SETPARITY, &uart_param);
	uart_param = UART__DEFAULT_STOPBITS;
	UartIOCtl(UART_SETSTOPBITS, &uart_param);
	uart_param = UART_DEFAULT_BAUD;
    UartIOCtl(UART_SETSPEED, &uart_param);
	
	UCSRB = BV(RXCIE) | BV(TXCIE) | BV(RXEN) | BV(TXEN);

	fdevopen(UartPutc, UartGetc, 0);
}

void
UartIOCtl(uint16_t req, void *conf)
{
 300:	cf 93       	push	r28
 302:	df 93       	push	r29
 304:	eb 01       	movw	r28, r22
    uint32_t *lvp = (uint32_t *)conf;
    uint32_t lv = *lvp;
 306:	28 81       	ld	r18, Y
 308:	39 81       	ldd	r19, Y+1	; 0x01
 30a:	4a 81       	ldd	r20, Y+2	; 0x02
 30c:	5b 81       	ldd	r21, Y+3	; 0x03
    uint8_t bv = (uint8_t)lv;
 30e:	62 2f       	mov	r22, r18
    uint16_t sv;

    switch (req)
 310:	71 e0       	ldi	r23, 0x01	; 1
 312:	84 30       	cpi	r24, 0x04	; 4
 314:	97 07       	cpc	r25, r23
 316:	09 f4       	brne	.+2      	; 0x31a
 318:	6b c0       	rjmp	.+214    	; 0x3f0
 31a:	71 e0       	ldi	r23, 0x01	; 1
 31c:	85 30       	cpi	r24, 0x05	; 5
 31e:	97 07       	cpc	r25, r23
 320:	68 f4       	brcc	.+26     	; 0x33c
 322:	71 e0       	ldi	r23, 0x01	; 1
 324:	82 30       	cpi	r24, 0x02	; 2
 326:	97 07       	cpc	r25, r23
 328:	d1 f1       	breq	.+116    	; 0x39e
 32a:	71 e0       	ldi	r23, 0x01	; 1
 32c:	83 30       	cpi	r24, 0x03	; 3
 32e:	97 07       	cpc	r25, r23
 330:	08 f0       	brcs	.+2      	; 0x334
 332:	53 c0       	rjmp	.+166    	; 0x3da
 334:	81 50       	subi	r24, 0x01	; 1
 336:	91 40       	sbci	r25, 0x01	; 1
 338:	a9 f0       	breq	.+42     	; 0x364
 33a:	8d c0       	rjmp	.+282    	; 0x456
 33c:	71 e0       	ldi	r23, 0x01	; 1
 33e:	86 30       	cpi	r24, 0x06	; 6
 340:	97 07       	cpc	r25, r23
 342:	09 f4       	brne	.+2      	; 0x346
 344:	68 c0       	rjmp	.+208    	; 0x416
 346:	21 e0       	ldi	r18, 0x01	; 1
 348:	86 30       	cpi	r24, 0x06	; 6
 34a:	92 07       	cpc	r25, r18
 34c:	08 f4       	brcc	.+2      	; 0x350
 34e:	58 c0       	rjmp	.+176    	; 0x400
 350:	71 e0       	ldi	r23, 0x01	; 1
 352:	87 30       	cpi	r24, 0x07	; 7
 354:	97 07       	cpc	r25, r23
 356:	09 f4       	brne	.+2      	; 0x35a
 358:	60 c0       	rjmp	.+192    	; 0x41a
 35a:	88 50       	subi	r24, 0x08	; 8
 35c:	91 40       	sbci	r25, 0x01	; 1
 35e:	09 f4       	brne	.+2      	; 0x362
 360:	68 c0       	rjmp	.+208    	; 0x432
 362:	79 c0       	rjmp	.+242    	; 0x456
	{
		case UART_SETSPEED:
		{
			sv = (uint16_t) ((((2UL * CPUCLK) / (lv * 16UL)) + 1UL) / 2UL) - 1;
 364:	f4 e0       	ldi	r31, 0x04	; 4
 366:	22 0f       	add	r18, r18
 368:	33 1f       	adc	r19, r19
 36a:	44 1f       	adc	r20, r20
 36c:	55 1f       	adc	r21, r21
 36e:	fa 95       	dec	r31
 370:	d1 f7       	brne	.-12     	; 0x366
 372:	60 e0       	ldi	r22, 0x00	; 0
 374:	70 e0       	ldi	r23, 0x00	; 0
 376:	81 ee       	ldi	r24, 0xE1	; 225
 378:	90 e0       	ldi	r25, 0x00	; 0
 37a:	0e 94 4e 06 	call	0xc9c
 37e:	da 01       	movw	r26, r20
 380:	c9 01       	movw	r24, r18
 382:	01 96       	adiw	r24, 0x01	; 1
 384:	a1 1d       	adc	r26, r1
 386:	b1 1d       	adc	r27, r1
 388:	b6 95       	lsr	r27
 38a:	a7 95       	ror	r26
 38c:	97 95       	ror	r25
 38e:	87 95       	ror	r24
 390:	9c 01       	movw	r18, r24
 392:	21 50       	subi	r18, 0x01	; 1
 394:	30 40       	sbci	r19, 0x00	; 0
			UBRRL = (uint8_t) sv;
 396:	29 b9       	out	0x09, r18	; 9
			UBRRH = (uint8_t) (sv >> 8);
 398:	83 2f       	mov	r24, r19
 39a:	99 27       	eor	r25, r25
 39c:	48 c0       	rjmp	.+144    	; 0x42e
		}
        break;

		case UART_GETSPEED:
		{
			sv = ((uint16_t)UBRRH << 8) || UBRRL;
 39e:	20 e0       	ldi	r18, 0x00	; 0
 3a0:	30 e0       	ldi	r19, 0x00	; 0
 3a2:	80 b5       	in	r24, 0x20	; 32
 3a4:	88 23       	and	r24, r24
 3a6:	19 f4       	brne	.+6      	; 0x3ae
 3a8:	89 b1       	in	r24, 0x09	; 9
 3aa:	88 23       	and	r24, r24
 3ac:	11 f0       	breq	.+4      	; 0x3b2
 3ae:	21 e0       	ldi	r18, 0x01	; 1
 3b0:	30 e0       	ldi	r19, 0x00	; 0
			*lvp = CPUCLK / (16UL * (uint32_t)(sv + 1));
 3b2:	2f 5f       	subi	r18, 0xFF	; 255
 3b4:	3f 4f       	sbci	r19, 0xFF	; 255
 3b6:	44 27       	eor	r20, r20
 3b8:	55 27       	eor	r21, r21
 3ba:	64 e0       	ldi	r22, 0x04	; 4
 3bc:	22 0f       	add	r18, r18
 3be:	33 1f       	adc	r19, r19
 3c0:	44 1f       	adc	r20, r20
 3c2:	55 1f       	adc	r21, r21
 3c4:	6a 95       	dec	r22
 3c6:	d1 f7       	brne	.-12     	; 0x3bc
 3c8:	60 e0       	ldi	r22, 0x00	; 0
 3ca:	70 e8       	ldi	r23, 0x80	; 128
 3cc:	80 e7       	ldi	r24, 0x70	; 112
 3ce:	90 e0       	ldi	r25, 0x00	; 0
 3d0:	0e 94 4e 06 	call	0xc9c
 3d4:	da 01       	movw	r26, r20
 3d6:	c9 01       	movw	r24, r18
 3d8:	3a c0       	rjmp	.+116    	; 0x44e
		}
        break;

		case UART_SETDATABITS:
		{
			if (bv >= 5 && bv <= 8)
 3da:	92 2f       	mov	r25, r18
 3dc:	95 50       	subi	r25, 0x05	; 5
 3de:	94 30       	cpi	r25, 0x04	; 4
 3e0:	d0 f5       	brcc	.+116    	; 0x456
			{
				bv = (bv - 5) << 1;
 3e2:	99 0f       	add	r25, r25
				UCSRC = (UCSRC & 0xF9) | bv;
 3e4:	80 b5       	in	r24, 0x20	; 32
 3e6:	89 7f       	andi	r24, 0xF9	; 249
 3e8:	89 2b       	or	r24, r25
 3ea:	80 bd       	out	0x20, r24	; 32
				UCSRB &= 0xFB;
 3ec:	52 98       	cbi	0x0a, 2	; 10
			}
		}
        break;
 3ee:	33 c0       	rjmp	.+102    	; 0x456

		case UART_GETDATABITS:
		{
			*lvp = ((UCSRC & 0x06) >> 1) + 5;
 3f0:	80 b5       	in	r24, 0x20	; 32
 3f2:	99 27       	eor	r25, r25
 3f4:	86 70       	andi	r24, 0x06	; 6
 3f6:	90 70       	andi	r25, 0x00	; 0
 3f8:	95 95       	asr	r25
 3fa:	87 95       	ror	r24
 3fc:	05 96       	adiw	r24, 0x05	; 5
 3fe:	23 c0       	rjmp	.+70     	; 0x446
		}
        break;

		case UART_SETPARITY:
		{
			if (bv <= 2)
 400:	63 30       	cpi	r22, 0x03	; 3
 402:	48 f5       	brcc	.+82     	; 0x456
			{
				if (bv == 1) bv = 3;
 404:	61 30       	cpi	r22, 0x01	; 1
 406:	09 f4       	brne	.+2      	; 0x40a
 408:	63 e0       	ldi	r22, 0x03	; 3
				bv <<= 4;
 40a:	62 95       	swap	r22
 40c:	60 7f       	andi	r22, 0xF0	; 240
				UCSRC = (UCSRC & 0xCF) | bv;
 40e:	80 b5       	in	r24, 0x20	; 32
 410:	8f 7c       	andi	r24, 0xCF	; 207
 412:	86 2b       	or	r24, r22
 414:	0c c0       	rjmp	.+24     	; 0x42e
			}
		}
		break;

		case UART_GETPARITY:
		{
			bv = (UCSRC & 0x30) >> 4;
 416:	80 b5       	in	r24, 0x20	; 32
 418:	1e c0       	rjmp	.+60     	; 0x456
			if (bv == 3) bv = 1;
		}
        break;

		case UART_SETSTOPBITS:
		{
			if (bv == 1 || bv == 2)
 41a:	96 2f       	mov	r25, r22
 41c:	91 50       	subi	r25, 0x01	; 1
 41e:	92 30       	cpi	r25, 0x02	; 2
 420:	d0 f4       	brcc	.+52     	; 0x456
			{
				bv = (bv - 1) << 3;
 422:	99 0f       	add	r25, r25
 424:	99 0f       	add	r25, r25
 426:	99 0f       	add	r25, r25
                UCSRC = (UCSRC & 0xF7) | bv;
 428:	80 b5       	in	r24, 0x20	; 32
 42a:	87 7f       	andi	r24, 0xF7	; 247
 42c:	89 2b       	or	r24, r25
 42e:	80 bd       	out	0x20, r24	; 32
			}
		}
        break;
 430:	12 c0       	rjmp	.+36     	; 0x456

		case UART_GETSTOPBITS:
		{
			*lvp = ((UCSRC & 0x08) >> 3) + 1;
 432:	80 b5       	in	r24, 0x20	; 32
 434:	99 27       	eor	r25, r25
 436:	88 70       	andi	r24, 0x08	; 8
 438:	90 70       	andi	r25, 0x00	; 0
 43a:	23 e0       	ldi	r18, 0x03	; 3
 43c:	95 95       	asr	r25
 43e:	87 95       	ror	r24
 440:	2a 95       	dec	r18
 442:	e1 f7       	brne	.-8      	; 0x43c
 444:	01 96       	adiw	r24, 0x01	; 1
 446:	aa 27       	eor	r26, r26
 448:	97 fd       	sbrc	r25, 7
 44a:	a0 95       	com	r26
 44c:	ba 2f       	mov	r27, r26
 44e:	88 83       	st	Y, r24
 450:	99 83       	std	Y+1, r25	; 0x01
 452:	aa 83       	std	Y+2, r26	; 0x02
 454:	bb 83       	std	Y+3, r27	; 0x03
 456:	df 91       	pop	r29
 458:	cf 91       	pop	r28
 45a:	08 95       	ret

0000045c <UartInit>:
 45c:	cf 93       	push	r28
 45e:	df 93       	push	r29
 460:	cd b7       	in	r28, 0x3d	; 61
 462:	de b7       	in	r29, 0x3e	; 62
 464:	24 97       	sbiw	r28, 0x04	; 4
 466:	0f b6       	in	r0, 0x3f	; 63
 468:	f8 94       	cli
 46a:	de bf       	out	0x3e, r29	; 62
 46c:	0f be       	out	0x3f, r0	; 63
 46e:	cd bf       	out	0x3d, r28	; 61
 470:	8b e8       	ldi	r24, 0x8B	; 139
 472:	91 e0       	ldi	r25, 0x01	; 1
 474:	0e 94 ad 05 	call	0xb5a
 478:	88 e8       	ldi	r24, 0x88	; 136
 47a:	91 e0       	ldi	r25, 0x01	; 1
 47c:	0e 94 ad 05 	call	0xb5a
 480:	88 e0       	ldi	r24, 0x08	; 8
 482:	90 e0       	ldi	r25, 0x00	; 0
 484:	a0 e0       	ldi	r26, 0x00	; 0
 486:	b0 e0       	ldi	r27, 0x00	; 0
 488:	89 83       	std	Y+1, r24	; 0x01
 48a:	9a 83       	std	Y+2, r25	; 0x02
 48c:	ab 83       	std	Y+3, r26	; 0x03
 48e:	bc 83       	std	Y+4, r27	; 0x04
 490:	be 01       	movw	r22, r28
 492:	6f 5f       	subi	r22, 0xFF	; 255
 494:	7f 4f       	sbci	r23, 0xFF	; 255
 496:	83 e0       	ldi	r24, 0x03	; 3
 498:	91 e0       	ldi	r25, 0x01	; 1
 49a:	0e 94 80 01 	call	0x300
 49e:	19 82       	std	Y+1, r1	; 0x01
 4a0:	1a 82       	std	Y+2, r1	; 0x02
 4a2:	1b 82       	std	Y+3, r1	; 0x03
 4a4:	1c 82       	std	Y+4, r1	; 0x04
 4a6:	be 01       	movw	r22, r28
 4a8:	6f 5f       	subi	r22, 0xFF	; 255
 4aa:	7f 4f       	sbci	r23, 0xFF	; 255
 4ac:	85 e0       	ldi	r24, 0x05	; 5
 4ae:	91 e0       	ldi	r25, 0x01	; 1
 4b0:	0e 94 80 01 	call	0x300
 4b4:	81 e0       	ldi	r24, 0x01	; 1
 4b6:	90 e0       	ldi	r25, 0x00	; 0
 4b8:	a0 e0       	ldi	r26, 0x00	; 0
 4ba:	b0 e0       	ldi	r27, 0x00	; 0
 4bc:	89 83       	std	Y+1, r24	; 0x01
 4be:	9a 83       	std	Y+2, r25	; 0x02
 4c0:	ab 83       	std	Y+3, r26	; 0x03
 4c2:	bc 83       	std	Y+4, r27	; 0x04
 4c4:	be 01       	movw	r22, r28
 4c6:	6f 5f       	subi	r22, 0xFF	; 255
 4c8:	7f 4f       	sbci	r23, 0xFF	; 255
 4ca:	87 e0       	ldi	r24, 0x07	; 7
 4cc:	91 e0       	ldi	r25, 0x01	; 1
 4ce:	0e 94 80 01 	call	0x300
 4d2:	80 e8       	ldi	r24, 0x80	; 128
 4d4:	95 e2       	ldi	r25, 0x25	; 37
 4d6:	a0 e0       	ldi	r26, 0x00	; 0
 4d8:	b0 e0       	ldi	r27, 0x00	; 0
 4da:	89 83       	std	Y+1, r24	; 0x01
 4dc:	9a 83       	std	Y+2, r25	; 0x02
 4de:	ab 83       	std	Y+3, r26	; 0x03
 4e0:	bc 83       	std	Y+4, r27	; 0x04
 4e2:	be 01       	movw	r22, r28
 4e4:	6f 5f       	subi	r22, 0xFF	; 255
 4e6:	7f 4f       	sbci	r23, 0xFF	; 255
 4e8:	81 e0       	ldi	r24, 0x01	; 1
 4ea:	91 e0       	ldi	r25, 0x01	; 1
 4ec:	0e 94 80 01 	call	0x300
 4f0:	88 ed       	ldi	r24, 0xD8	; 216
 4f2:	8a b9       	out	0x0a, r24	; 10
 4f4:	40 e0       	ldi	r20, 0x00	; 0
 4f6:	50 e0       	ldi	r21, 0x00	; 0
 4f8:	63 e2       	ldi	r22, 0x23	; 35
 4fa:	71 e0       	ldi	r23, 0x01	; 1
 4fc:	8d e4       	ldi	r24, 0x4D	; 77
 4fe:	91 e0       	ldi	r25, 0x01	; 1
 500:	0e 94 8b 02 	call	0x516
 504:	24 96       	adiw	r28, 0x04	; 4
 506:	0f b6       	in	r0, 0x3f	; 63
 508:	f8 94       	cli
 50a:	de bf       	out	0x3e, r29	; 62
 50c:	0f be       	out	0x3f, r0	; 63
 50e:	cd bf       	out	0x3d, r28	; 61
 510:	df 91       	pop	r29
 512:	cf 91       	pop	r28
 514:	08 95       	ret

00000516 <fdevopen>:
 516:	0f 93       	push	r16
 518:	1f 93       	push	r17
 51a:	cf 93       	push	r28
 51c:	df 93       	push	r29
 51e:	8c 01       	movw	r16, r24
 520:	eb 01       	movw	r28, r22
 522:	00 97       	sbiw	r24, 0x00	; 0
 524:	a1 f1       	breq	.+104    	; 0x58e
 526:	6c e0       	ldi	r22, 0x0C	; 12
 528:	70 e0       	ldi	r23, 0x00	; 0
 52a:	81 e0       	ldi	r24, 0x01	; 1
 52c:	90 e0       	ldi	r25, 0x00	; 0
 52e:	0e 94 12 03 	call	0x624
 532:	fc 01       	movw	r30, r24
 534:	89 2b       	or	r24, r25
 536:	21 f1       	breq	.+72     	; 0x580
 538:	20 97       	sbiw	r28, 0x00	; 0
 53a:	51 f0       	breq	.+20     	; 0x550
 53c:	c2 87       	std	Z+10, r28	; 0x0a
 53e:	d3 87       	std	Z+11, r29	; 0x0b
 540:	21 e0       	ldi	r18, 0x01	; 1
 542:	23 83       	std	Z+3, r18	; 0x03
 544:	80 91 03 02 	lds	r24, 0x0203
 548:	90 91 04 02 	lds	r25, 0x0204
 54c:	89 2b       	or	r24, r25
 54e:	d1 f0       	breq	.+52     	; 0x584
 550:	01 15       	cp	r16, r1
 552:	11 05       	cpc	r17, r1
 554:	a9 f0       	breq	.+42     	; 0x580
 556:	00 87       	std	Z+8, r16	; 0x08
 558:	11 87       	std	Z+9, r17	; 0x09
 55a:	03 81       	ldd	r16, Z+3	; 0x03
 55c:	02 60       	ori	r16, 0x02	; 2
 55e:	03 83       	std	Z+3, r16	; 0x03
 560:	a0 91 05 02 	lds	r26, 0x0205
 564:	b0 91 06 02 	lds	r27, 0x0206
 568:	ab 2b       	or	r26, r27
 56a:	51 f4       	brne	.+20     	; 0x580
 56c:	f0 93 06 02 	sts	0x0206, r31
 570:	e0 93 05 02 	sts	0x0205, r30
 574:	c0 91 07 02 	lds	r28, 0x0207
 578:	d0 91 08 02 	lds	r29, 0x0208
 57c:	cd 2b       	or	r28, r29
 57e:	51 f0       	breq	.+20     	; 0x594
 580:	cf 01       	movw	r24, r30
 582:	0d c0       	rjmp	.+26     	; 0x59e
 584:	f0 93 04 02 	sts	0x0204, r31
 588:	e0 93 03 02 	sts	0x0203, r30
 58c:	e1 cf       	rjmp	.-62     	; 0x550
 58e:	67 2b       	or	r22, r23
 590:	51 f6       	brne	.-108    	; 0x526
 592:	05 c0       	rjmp	.+10     	; 0x59e
 594:	f0 93 08 02 	sts	0x0208, r31
 598:	e0 93 07 02 	sts	0x0207, r30
 59c:	f1 cf       	rjmp	.-30     	; 0x580
 59e:	df 91       	pop	r29
 5a0:	cf 91       	pop	r28
 5a2:	1f 91       	pop	r17
 5a4:	0f 91       	pop	r16
 5a6:	08 95       	ret

000005a8 <puts_P>:
 5a8:	0f 93       	push	r16
 5aa:	1f 93       	push	r17
 5ac:	cf 93       	push	r28
 5ae:	df 93       	push	r29
 5b0:	9c 01       	movw	r18, r24
 5b2:	00 e0       	ldi	r16, 0x00	; 0
 5b4:	10 e0       	ldi	r17, 0x00	; 0
 5b6:	a0 91 05 02 	lds	r26, 0x0205
 5ba:	b0 91 06 02 	lds	r27, 0x0206
 5be:	ed 01       	movw	r28, r26
 5c0:	8b 81       	ldd	r24, Y+3	; 0x03
 5c2:	81 ff       	sbrs	r24, 1
 5c4:	28 c0       	rjmp	.+80     	; 0x616
 5c6:	e9 01       	movw	r28, r18
 5c8:	21 96       	adiw	r28, 0x01	; 1
 5ca:	f9 01       	movw	r30, r18
 5cc:	84 91       	lpm	r24, Z
 5ce:	88 23       	and	r24, r24
 5d0:	29 f4       	brne	.+10     	; 0x5dc
 5d2:	16 c0       	rjmp	.+44     	; 0x600
 5d4:	a0 91 05 02 	lds	r26, 0x0205
 5d8:	b0 91 06 02 	lds	r27, 0x0206
 5dc:	fd 01       	movw	r30, r26
 5de:	20 85       	ldd	r18, Z+8	; 0x08
 5e0:	31 85       	ldd	r19, Z+9	; 0x09
 5e2:	f9 01       	movw	r30, r18
 5e4:	09 95       	icall
 5e6:	89 2b       	or	r24, r25
 5e8:	11 f0       	breq	.+4      	; 0x5ee
 5ea:	0f ef       	ldi	r16, 0xFF	; 255
 5ec:	1f ef       	ldi	r17, 0xFF	; 255
 5ee:	fe 01       	movw	r30, r28
 5f0:	21 96       	adiw	r28, 0x01	; 1
 5f2:	84 91       	lpm	r24, Z
 5f4:	88 23       	and	r24, r24
 5f6:	71 f7       	brne	.-36     	; 0x5d4
 5f8:	a0 91 05 02 	lds	r26, 0x0205
 5fc:	b0 91 06 02 	lds	r27, 0x0206
 600:	ed 01       	movw	r28, r26
 602:	e8 85       	ldd	r30, Y+8	; 0x08
 604:	f9 85       	ldd	r31, Y+9	; 0x09
 606:	8a e0       	ldi	r24, 0x0A	; 10
 608:	09 95       	icall
 60a:	89 2b       	or	r24, r25
 60c:	11 f0       	breq	.+4      	; 0x612
 60e:	0f ef       	ldi	r16, 0xFF	; 255
 610:	1f ef       	ldi	r17, 0xFF	; 255
 612:	c8 01       	movw	r24, r16

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