📄 uart.lst
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543 024e 5298 cbi 42-0x20,2
176:uart.c **** }
177:uart.c **** }
178:uart.c **** break;
545 .LM60:
546 0250 33C0 rjmp .L20
547 .L28:
179:uart.c ****
180:uart.c **** case UART_GETDATABITS:
181:uart.c **** {
182:uart.c **** *lvp = ((UCSRC & 0x06) >> 1) + 5;
549 .LM61:
550 0252 80B5 in r24,64-0x20
551 0254 9927 clr r25
552 0256 8670 andi r24,lo8(6)
553 0258 9070 andi r25,hi8(6)
554 025a 9595 asr r25
555 025c 8795 ror r24
556 025e 0596 adiw r24,5
557 0260 23C0 rjmp .L39
558 .L29:
183:uart.c **** }
184:uart.c **** break;
185:uart.c ****
186:uart.c **** case UART_SETPARITY:
187:uart.c **** {
188:uart.c **** if (bv <= 2)
560 .LM62:
561 0262 6330 cpi r22,lo8(3)
562 0264 48F5 brsh .L20
189:uart.c **** {
190:uart.c **** if (bv == 1) bv = 3;
564 .LM63:
565 0266 6130 cpi r22,lo8(1)
566 0268 09F4 brne .L31
567 026a 63E0 ldi r22,lo8(3)
568 .L31:
191:uart.c **** bv <<= 4;
570 .LM64:
571 026c 6295 swap r22
572 026e 607F andi r22,0xf0
192:uart.c **** UCSRC = (UCSRC & 0xCF) | bv;
574 .LM65:
575 0270 80B5 in r24,64-0x20
576 0272 8F7C andi r24,lo8(-49)
577 0274 862B or r24,r22
578 0276 0CC0 rjmp .L38
579 .L32:
193:uart.c **** }
194:uart.c **** }
195:uart.c **** break;
196:uart.c ****
197:uart.c **** case UART_GETPARITY:
198:uart.c **** {
199:uart.c **** bv = (UCSRC & 0x30) >> 4;
581 .LM66:
582 0278 80B5 in r24,64-0x20
583 027a 1EC0 rjmp .L20
584 .L34:
200:uart.c **** if (bv == 3) bv = 1;
201:uart.c **** }
202:uart.c **** break;
203:uart.c ****
204:uart.c **** case UART_SETSTOPBITS:
205:uart.c **** {
206:uart.c **** if (bv == 1 || bv == 2)
586 .LM67:
587 027c 962F mov r25,r22
588 027e 9150 subi r25,lo8(-(-1))
589 0280 9230 cpi r25,lo8(2)
590 0282 D0F4 brsh .L20
207:uart.c **** {
208:uart.c **** bv = (bv - 1) << 3;
592 .LM68:
593 0284 990F lsl r25
594 0286 990F lsl r25
595 0288 990F lsl r25
209:uart.c **** UCSRC = (UCSRC & 0xF7) | bv;
597 .LM69:
598 028a 80B5 in r24,64-0x20
599 028c 877F andi r24,lo8(-9)
600 028e 892B or r24,r25
601 .L38:
602 0290 80BD out 64-0x20,r24
210:uart.c **** }
211:uart.c **** }
212:uart.c **** break;
604 .LM70:
605 0292 12C0 rjmp .L20
606 .L36:
213:uart.c ****
214:uart.c **** case UART_GETSTOPBITS:
215:uart.c **** {
216:uart.c **** *lvp = ((UCSRC & 0x08) >> 3) + 1;
608 .LM71:
609 0294 80B5 in r24,64-0x20
610 0296 9927 clr r25
611 0298 8870 andi r24,lo8(8)
612 029a 9070 andi r25,hi8(8)
613 029c 23E0 ldi r18,3
614 029e 9595 1: asr r25
615 02a0 8795 ror r24
616 02a2 2A95 dec r18
617 02a4 E1F7 brne 1b
618 02a6 0196 adiw r24,1
619 .L39:
620 02a8 AA27 clr r26
621 02aa 97FD sbrc r25,7
622 02ac A095 com r26
623 02ae BA2F mov r27,r26
624 .L40:
625 02b0 8883 st Y,r24
626 02b2 9983 std Y+1,r25
627 02b4 AA83 std Y+2,r26
628 02b6 BB83 std Y+3,r27
629 .L20:
630 /* epilogue: frame size=0 */
631 02b8 DF91 pop r29
632 02ba CF91 pop r28
633 02bc 0895 ret
634 /* epilogue end (size=3) */
635 /* function UartIOCtl size 176 (171) */
643 .Lscope4:
645 .global UartInit
647 UartInit:
649 .LM72:
650 /* prologue: frame size=4 */
651 02be CF93 push r28
652 02c0 DF93 push r29
653 02c2 CDB7 in r28,__SP_L__
654 02c4 DEB7 in r29,__SP_H__
655 02c6 2497 sbiw r28,4
656 02c8 0FB6 in __tmp_reg__,__SREG__
657 02ca F894 cli
658 02cc DEBF out __SP_H__,r29
659 02ce 0FBE out __SREG__,__tmp_reg__
660 02d0 CDBF out __SP_L__,r28
661 /* prologue end (size=10) */
663 .LM73:
664 02d2 80E0 ldi r24,lo8(rx_rdy)
665 02d4 90E0 ldi r25,hi8(rx_rdy)
666 02d6 0E94 0000 call AvrXResetSemaphore
668 .LM74:
669 02da 80E0 ldi r24,lo8(tx_rdy)
670 02dc 90E0 ldi r25,hi8(tx_rdy)
671 02de 0E94 0000 call AvrXResetSemaphore
673 .LM75:
674 02e2 88E0 ldi r24,lo8(8)
675 02e4 90E0 ldi r25,hi8(8)
676 02e6 A0E0 ldi r26,hlo8(8)
677 02e8 B0E0 ldi r27,hhi8(8)
678 02ea 8983 std Y+1,r24
679 02ec 9A83 std Y+2,r25
680 02ee AB83 std Y+3,r26
681 02f0 BC83 std Y+4,r27
683 .LM76:
684 02f2 BE01 movw r22,r28
685 02f4 6F5F subi r22,lo8(-(1))
686 02f6 7F4F sbci r23,hi8(-(1))
687 02f8 83E0 ldi r24,lo8(259)
688 02fa 91E0 ldi r25,hi8(259)
689 02fc 0E94 0000 call UartIOCtl
691 .LM77:
692 0300 1982 std Y+1,__zero_reg__
693 0302 1A82 std Y+2,__zero_reg__
694 0304 1B82 std Y+3,__zero_reg__
695 0306 1C82 std Y+4,__zero_reg__
697 .LM78:
698 0308 BE01 movw r22,r28
699 030a 6F5F subi r22,lo8(-(1))
700 030c 7F4F sbci r23,hi8(-(1))
701 030e 85E0 ldi r24,lo8(261)
702 0310 91E0 ldi r25,hi8(261)
703 0312 0E94 0000 call UartIOCtl
705 .LM79:
706 0316 81E0 ldi r24,lo8(1)
707 0318 90E0 ldi r25,hi8(1)
708 031a A0E0 ldi r26,hlo8(1)
709 031c B0E0 ldi r27,hhi8(1)
710 031e 8983 std Y+1,r24
711 0320 9A83 std Y+2,r25
712 0322 AB83 std Y+3,r26
713 0324 BC83 std Y+4,r27
715 .LM80:
716 0326 BE01 movw r22,r28
717 0328 6F5F subi r22,lo8(-(1))
718 032a 7F4F sbci r23,hi8(-(1))
719 032c 87E0 ldi r24,lo8(263)
720 032e 91E0 ldi r25,hi8(263)
721 0330 0E94 0000 call UartIOCtl
723 .LM81:
724 0334 80E8 ldi r24,lo8(9600)
725 0336 95E2 ldi r25,hi8(9600)
726 0338 A0E0 ldi r26,hlo8(9600)
727 033a B0E0 ldi r27,hhi8(9600)
728 033c 8983 std Y+1,r24
729 033e 9A83 std Y+2,r25
730 0340 AB83 std Y+3,r26
731 0342 BC83 std Y+4,r27
733 .LM82:
734 0344 BE01 movw r22,r28
735 0346 6F5F subi r22,lo8(-(1))
736 0348 7F4F sbci r23,hi8(-(1))
737 034a 81E0 ldi r24,lo8(257)
738 034c 91E0 ldi r25,hi8(257)
739 034e 0E94 0000 call UartIOCtl
741 .LM83:
742 0352 88ED ldi r24,lo8(-40)
743 0354 8AB9 out 42-0x20,r24
745 .LM84:
746 0356 40E0 ldi r20,lo8(0)
747 0358 50E0 ldi r21,hi8(0)
748 035a 60E0 ldi r22,lo8(pm(UartGetc))
749 035c 70E0 ldi r23,hi8(pm(UartGetc))
750 035e 80E0 ldi r24,lo8(pm(UartPutc))
751 0360 90E0 ldi r25,hi8(pm(UartPutc))
752 0362 0E94 0000 call fdevopen
753 /* epilogue: frame size=4 */
754 0366 2496 adiw r28,4
755 0368 0FB6 in __tmp_reg__,__SREG__
756 036a F894 cli
757 036c DEBF out __SP_H__,r29
758 036e 0FBE out __SREG__,__tmp_reg__
759 0370 CDBF out __SP_L__,r28
760 0372 DF91 pop r29
761 0374 CF91 pop r28
762 0376 0895 ret
763 /* epilogue end (size=9) */
764 /* function UartInit size 93 (74) */
769 .Lscope5:
770 .comm rx_buffer,50,1
771 .comm rx_wr,1,1
772 .comm rx_count,1,1
773 .comm rx_rd,1,1
774 .comm rx_rdy,2,1
775 .comm rx_buffer_overflow,1,1
776 .comm tx_buffer,50,1
777 .comm tx_wr,1,1
778 .comm tx_rd,1,1
779 .comm tx_count,1,1
780 .comm tx_rdy,2,1
792 .text
794 Letext:
795 /* File "uart.c": code 458 = 0x01ca ( 428), prologues 14, epilogues 16 */
DEFINED SYMBOLS
*ABS*:00000000 uart.c
*ABS*:0000003f __SREG__
*ABS*:0000003e __SP_H__
*ABS*:0000003d __SP_L__
*ABS*:00000000 __tmp_reg__
*ABS*:00000001 __zero_reg__
C:\DOCUME~1\KAIFA\LOCALS~1\Temp/ccs9aaaa.s:83 .text:00000000 __vector_11
*COM*:00000001 rx_wr
*COM*:00000032 rx_buffer
*COM*:00000001 rx_count
*COM*:00000001 rx_buffer_overflow
*COM*:00000002 rx_rdy
C:\DOCUME~1\KAIFA\LOCALS~1\Temp/ccs9aaaa.s:164 .text:00000060 __vector_13
*COM*:00000001 tx_count
*COM*:00000001 tx_rd
*COM*:00000032 tx_buffer
*COM*:00000002 tx_rdy
C:\DOCUME~1\KAIFA\LOCALS~1\Temp/ccs9aaaa.s:220 .text:000000a8 UartGetc
*COM*:00000001 rx_rd
C:\DOCUME~1\KAIFA\LOCALS~1\Temp/ccs9aaaa.s:299 .text:000000fc UartPutc
*COM*:00000001 tx_wr
C:\DOCUME~1\KAIFA\LOCALS~1\Temp/ccs9aaaa.s:390 .text:00000162 UartIOCtl
C:\DOCUME~1\KAIFA\LOCALS~1\Temp/ccs9aaaa.s:647 .text:000002be UartInit
C:\DOCUME~1\KAIFA\LOCALS~1\Temp/ccs9aaaa.s:794 .text:00000378 Letext
UNDEFINED SYMBOLS
__do_copy_data
__do_clear_bss
IntProlog
AvrXIntSetSemaphore
Epilog
AvrXWaitSemaphore
AvrXResetSemaphore
__udivmodsi4
fdevopen
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