📄 veryhardd.rpt
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- 3 - C 20 OR2 s 0 4 0 1 ~3154~2
- 6 - C 23 OR2 s 0 4 0 1 ~3160~1
- 3 - C 23 OR2 s 0 4 0 1 ~3166~1
- 4 - C 17 OR2 s 0 4 0 1 ~3172~1
- 5 - C 16 OR2 s 0 4 0 1 ~3178~1
- 7 - C 16 OR2 s 0 4 0 1 ~3184~1
- 8 - C 13 OR2 s 0 4 0 1 ~3190~1
- 7 - C 24 OR2 s 0 4 0 1 ~3196~1
- 5 - C 24 OR2 s 0 4 0 1 ~3202~1
- 7 - C 13 OR2 s 0 4 0 1 ~3208~1
- 7 - C 11 OR2 s 0 4 0 1 ~3214~1
- 5 - C 11 OR2 s 0 4 0 1 ~3220~1
- 2 - C 12 OR2 s 0 4 0 1 ~3226~1
- 7 - C 10 OR2 s 0 4 0 1 ~3232~1
- 1 - C 10 OR2 s 0 4 0 1 ~3238~1
- 8 - C 08 OR2 s 0 4 0 1 ~3244~1
- 6 - C 08 OR2 s 0 4 0 1 ~3250~1
- 4 - C 08 OR2 s 0 4 0 1 ~3256~1
- 7 - C 09 OR2 s 0 4 0 1 ~3262~1
- 5 - C 09 OR2 s 0 4 0 1 ~3268~1
- 5 - C 10 OR2 s 0 4 0 1 ~3274~1
- 6 - C 19 OR2 s 0 4 0 1 ~3280~1
- 7 - C 19 OR2 s 0 4 0 1 ~3286~1
- 5 - C 13 OR2 s 0 4 0 1 ~3292~1
- 7 - C 14 OR2 s 0 4 0 1 ~3298~1
- 6 - C 14 OR2 s 0 4 0 1 ~3304~1
- 6 - C 13 OR2 s 0 4 0 1 ~3310~1
- 7 - C 15 OR2 s 0 4 0 1 ~3316~1
- 5 - C 15 OR2 s 0 4 0 1 ~3322~1
- 2 - C 17 OR2 s 0 4 0 1 ~3328~1
- 7 - C 17 OR2 s 0 4 0 1 ~3334~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\program\dianti\veryhardd.rpt
veryhardd
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 0/ 48( 0%) 30/ 48( 62%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
B: 5/ 96( 5%) 15/ 48( 31%) 3/ 48( 6%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 16/ 96( 16%) 11/ 48( 22%) 18/ 48( 37%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\program\dianti\veryhardd.rpt
veryhardd
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 83 clk
Device-Specific Information: e:\program\dianti\veryhardd.rpt
veryhardd
** EQUATIONS **
clk : INPUT;
down2 : INPUT;
down3 : INPUT;
k1 : INPUT;
k2 : INPUT;
k3 : INPUT;
up1 : INPUT;
up2 : INPUT;
-- Node name is 'a1'
-- Equation name is 'a1', type is output
a1 = tingl1;
-- Node name is 'a2'
-- Equation name is 'a2', type is output
a2 = tingl2;
-- Node name is 'a3'
-- Equation name is 'a3', type is output
a3 = tingl3;
-- Node name is ':52' = 'cengl1'
-- Equation name is 'cengl1', location is LC2_A22, type is buried.
cengl1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC1_B1 & !state0 & !state1
# cengl1 & state0 & state1
# cengl1 & !state0 & !state1
# cengl1 & _LC1_B1;
-- Node name is ':51' = 'cengl2'
-- Equation name is 'cengl2', location is LC8_A22, type is buried.
cengl2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !_LC1_B1 & state0 & !state1
# cengl2 & state0
# cengl2 & _LC1_B1;
-- Node name is ':50' = 'cengl3'
-- Equation name is 'cengl3', location is LC5_A24, type is buried.
cengl3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = cengl3 & _LC1_A17
# _LC1_A17 & _LC6_A22
# cengl3 & _LC1_B1;
-- Node name is ':49' = 'cnt10'
-- Equation name is 'cnt10', location is LC1_B6, type is buried.
cnt10 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !cnt10 & _LC1_B1;
-- Node name is ':48' = 'cnt11'
-- Equation name is 'cnt11', location is LC5_B6, type is buried.
cnt11 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !cnt10 & cnt11 & _LC1_B1
# cnt10 & !cnt11 & _LC1_B1;
-- Node name is ':47' = 'cnt12'
-- Equation name is 'cnt12', location is LC6_B5, type is buried.
cnt12 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = cnt12 & _LC1_B1 & !_LC4_B6
# !cnt12 & _LC1_B1 & _LC4_B6;
-- Node name is ':46' = 'cnt13'
-- Equation name is 'cnt13', location is LC4_B5, type is buried.
cnt13 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !cnt12 & cnt13 & _LC1_B1
# cnt13 & _LC1_B1 & !_LC4_B6
# cnt12 & !cnt13 & _LC1_B1 & _LC4_B6;
-- Node name is ':45' = 'cnt14'
-- Equation name is 'cnt14', location is LC5_B5, type is buried.
cnt14 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = cnt14 & _LC1_B1 & !_LC2_B5
# !cnt14 & _LC1_B1 & _LC2_B5;
-- Node name is ':44' = 'cnt15'
-- Equation name is 'cnt15', location is LC3_B8, type is buried.
cnt15 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = cnt15 & _LC1_B1 & !_LC1_B5
# !cnt15 & _LC1_B1 & _LC1_B5;
-- Node name is ':43' = 'cnt16'
-- Equation name is 'cnt16', location is LC4_B8, type is buried.
cnt16 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !cnt15 & cnt16 & _LC1_B1
# cnt16 & _LC1_B1 & !_LC1_B5
# cnt15 & !cnt16 & _LC1_B1 & _LC1_B5;
-- Node name is ':42' = 'cnt17'
-- Equation name is 'cnt17', location is LC6_B8, type is buried.
cnt17 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = cnt17 & _LC1_B1 & !_LC5_B8
# !cnt17 & _LC1_B1 & _LC5_B8;
-- Node name is ':41' = 'cnt18'
-- Equation name is 'cnt18', location is LC3_B11, type is buried.
cnt18 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = cnt18 & _LC1_B1 & !_LC1_B8
# !cnt18 & _LC1_B1 & _LC1_B8;
-- Node name is ':40' = 'cnt19'
-- Equation name is 'cnt19', location is LC7_B11, type is buried.
cnt19 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !cnt18 & cnt19 & _LC1_B1
# cnt19 & _LC1_B1 & !_LC1_B8
# cnt18 & !cnt19 & _LC1_B1 & _LC1_B8;
-- Node name is ':99' = 'cnt20'
-- Equation name is 'cnt20', location is LC5_C17, type is buried.
cnt20 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = !cnt20 & _LC6_C17
# cnt20 & !_LC1_A17
# cnt20 & _LC6_A22;
-- Node name is ':98' = 'cnt21'
-- Equation name is 'cnt21', location is LC8_C17, type is buried.
cnt21 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = cnt21 & _LC7_C17
# cnt20 & !cnt21 & _LC6_C17;
-- Node name is ':97' = 'cnt22'
-- Equation name is 'cnt22', location is LC3_C17, type is buried.
cnt22 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = !cnt22 & !_LC1_C17 & _LC6_C17
# cnt22 & _LC2_C17;
-- Node name is ':96' = 'cnt23'
-- Equation name is 'cnt23', location is LC6_C15, type is buried.
cnt23 = DFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = cnt23 & _LC5_C15
# !cnt23 & _LC3_C15 & _LC6_C17;
-- Node name is ':95' = 'cnt24'
-- Equation name is 'cnt24', location is LC8_C15, type is buried.
cnt24 = DFFE( _EQ018, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = cnt24 & _LC7_C15
# !cnt24 & _LC4_C15 & _LC6_C17;
-- Node name is ':94' = 'cnt25'
-- Equation name is 'cnt25', location is LC1_C13, type is buried.
cnt25 = DFFE( _EQ019, GLOBAL( clk), VCC, VCC, VCC);
_EQ019 = !cnt25 & _LC1_C15 & _LC6_C17
# cnt25 & _LC6_C13;
-- Node name is ':93' = 'cnt26'
-- Equation name is 'cnt26', location is LC3_C14, type is buried.
cnt26 = DFFE( _EQ020, GLOBAL( clk), VCC, VCC, VCC);
_EQ020 = cnt26 & _LC6_C14
# !cnt26 & _LC4_C14 & _LC6_C17;
-- Node name is ':92' = 'cnt27'
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