veryhardd.rpt
来自「这是一个用VHDL语言编写的电梯控制程序」· RPT 代码 · 共 1,260 行 · 第 1/5 页
RPT
1,260 行
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\program\dianti\veryhardd.rpt
veryhardd
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
18 - - A -- OUTPUT 0 1 0 0 a1
19 - - A -- OUTPUT 0 1 0 0 a2
73 - - A -- OUTPUT 0 1 0 0 a3
81 - - - 22 OUTPUT 0 1 0 0 door
71 - - A -- OUTPUT 0 1 0 0 mode
72 - - A -- OUTPUT 0 1 0 0 site1
69 - - A -- OUTPUT 0 1 0 0 site2
70 - - A -- OUTPUT 0 1 0 0 site3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\program\dianti\veryhardd.rpt
veryhardd
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - B 06 AND2 0 2 0 4 |LPM_ADD_SUB:642|addcore:adder|:167
- 2 - B 05 AND2 0 3 0 1 |LPM_ADD_SUB:642|addcore:adder|:175
- 1 - B 05 AND2 0 4 0 4 |LPM_ADD_SUB:642|addcore:adder|:179
- 5 - B 08 AND2 0 3 0 1 |LPM_ADD_SUB:642|addcore:adder|:187
- 1 - B 08 AND2 0 4 0 3 |LPM_ADD_SUB:642|addcore:adder|:191
- 1 - B 11 AND2 0 3 0 4 |LPM_ADD_SUB:642|addcore:adder|:199
- 5 - B 11 AND2 0 2 0 1 |LPM_ADD_SUB:642|addcore:adder|:203
- 2 - B 11 AND2 0 4 0 2 |LPM_ADD_SUB:642|addcore:adder|:211
- 4 - B 10 AND2 0 2 0 3 |LPM_ADD_SUB:642|addcore:adder|:215
- 2 - B 10 AND2 0 3 0 3 |LPM_ADD_SUB:642|addcore:adder|:223
- 3 - B 19 AND2 0 3 0 4 |LPM_ADD_SUB:642|addcore:adder|:231
- 2 - B 19 AND2 0 3 0 1 |LPM_ADD_SUB:642|addcore:adder|:239
- 1 - B 19 AND2 0 4 0 4 |LPM_ADD_SUB:642|addcore:adder|:243
- 6 - B 23 AND2 0 2 0 1 |LPM_ADD_SUB:642|addcore:adder|:247
- 1 - B 23 AND2 0 4 0 3 |LPM_ADD_SUB:642|addcore:adder|:255
- 5 - B 12 AND2 0 3 0 3 |LPM_ADD_SUB:642|addcore:adder|:263
- 1 - B 12 AND2 0 3 0 3 |LPM_ADD_SUB:642|addcore:adder|:271
- 6 - B 01 AND2 0 3 0 2 |LPM_ADD_SUB:642|addcore:adder|:279
- 3 - C 15 OR2 ! 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:171
- 4 - C 15 OR2 ! 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:175
- 1 - C 15 OR2 ! 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:179
- 4 - C 14 OR2 ! 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:183
- 5 - C 14 OR2 ! 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:187
- 1 - C 14 OR2 ! 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:191
- 3 - C 19 OR2 ! 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:195
- 5 - C 19 OR2 ! 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:199
- 1 - C 19 OR2 ! 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:203
- 3 - C 09 OR2 ! 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:207
- 4 - C 09 OR2 ! 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:211
- 1 - C 09 OR2 ! 0 2 0 5 |LPM_ADD_SUB:1952|addcore:adder|:215
- 5 - C 08 OR2 ! 0 2 0 2 |LPM_ADD_SUB:1952|addcore:adder|:219
- 7 - C 08 OR2 ! 0 3 0 2 |LPM_ADD_SUB:1952|addcore:adder|:223
- 4 - C 03 AND2 0 4 0 3 |LPM_ADD_SUB:1952|addcore:adder|:227
- 6 - C 10 AND2 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:231
- 8 - C 10 AND2 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:235
- 3 - C 11 AND2 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:239
- 4 - C 11 AND2 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:243
- 1 - C 11 AND2 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:247
- 1 - C 24 AND2 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:251
- 4 - C 24 AND2 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:255
- 3 - C 24 AND2 0 2 0 4 |LPM_ADD_SUB:1952|addcore:adder|:259
- 1 - C 16 AND2 0 2 0 3 |LPM_ADD_SUB:1952|addcore:adder|:263
- 4 - C 16 AND2 0 2 0 2 |LPM_ADD_SUB:1952|addcore:adder|:267
- 3 - C 16 OR2 ! 0 4 0 5 |LPM_ADD_SUB:1952|addcore:adder|:271
- 2 - C 23 OR2 ! 0 2 0 2 |LPM_ADD_SUB:1952|addcore:adder|:275
- 4 - C 23 AND2 0 3 0 2 |LPM_ADD_SUB:1952|addcore:adder|:279
- 1 - A 22 DFFE + 0 3 1 0 :16
- 8 - B 01 DFFE + 0 3 0 1 cnt131 (:18)
- 7 - B 01 DFFE + 0 2 0 2 cnt130 (:19)
- 5 - B 01 DFFE + 0 3 0 2 cnt129 (:20)
- 4 - B 01 DFFE + 0 2 0 3 cnt128 (:21)
- 7 - B 12 DFFE + 0 3 0 2 cnt127 (:22)
- 6 - B 12 DFFE + 0 2 0 3 cnt126 (:23)
- 4 - B 12 DFFE + 0 3 0 2 cnt125 (:24)
- 3 - B 12 DFFE + 0 2 0 3 cnt124 (:25)
- 7 - B 23 DFFE + 0 3 0 2 cnt123 (:26)
- 5 - B 23 DFFE + 0 3 0 3 cnt122 (:27)
- 4 - B 23 DFFE + 0 2 0 4 cnt121 (:28)
- 3 - B 23 DFFE + 0 2 0 2 cnt120 (:29)
- 7 - B 19 DFFE + 0 3 0 3 cnt119 (:30)
- 6 - B 19 DFFE + 0 2 0 4 cnt118 (:31)
- 5 - B 19 DFFE + 0 3 0 2 cnt117 (:32)
- 4 - B 19 DFFE + 0 2 0 3 cnt116 (:33)
- 7 - B 10 DFFE + 0 3 0 2 cnt115 (:34)
- 6 - B 10 DFFE + 0 2 0 3 cnt114 (:35)
- 5 - B 10 DFFE + 0 2 0 2 cnt113 (:36)
- 1 - B 10 DFFE + 0 3 0 2 cnt112 (:37)
- 6 - B 11 DFFE + 0 3 0 3 cnt111 (:38)
- 8 - B 11 DFFE + 0 2 0 4 cnt110 (:39)
- 7 - B 11 DFFE + 0 3 0 2 cnt19 (:40)
- 3 - B 11 DFFE + 0 2 0 3 cnt18 (:41)
- 6 - B 08 DFFE + 0 2 0 2 cnt17 (:42)
- 4 - B 08 DFFE + 0 3 0 3 cnt16 (:43)
- 3 - B 08 DFFE + 0 2 0 4 cnt15 (:44)
- 5 - B 05 DFFE + 0 2 0 2 cnt14 (:45)
- 4 - B 05 DFFE + 0 3 0 3 cnt13 (:46)
- 6 - B 05 DFFE + 0 2 0 4 cnt12 (:47)
- 5 - B 06 DFFE + 0 2 0 2 cnt11 (:48)
- 1 - B 06 DFFE + 0 1 0 2 cnt10 (:49)
- 5 - A 24 DFFE + 0 3 1 2 cengl3 (:50)
- 8 - A 22 DFFE + 0 3 1 2 cengl2 (:51)
- 2 - A 22 DFFE + 0 3 1 2 cengl1 (:52)
- 7 - A 20 DFFE + 0 3 0 1 z (:53)
- 3 - A 24 DFFE + 0 2 0 8 state1 (:54)
- 5 - A 22 DFFE + 0 2 0 8 state0 (:55)
- 1 - A 15 DFFE + 1 1 1 1 tingl3 (:56)
- 6 - A 18 DFFE + 1 1 1 2 tingl2 (:57)
- 5 - A 23 DFFE + 1 2 1 1 tingl1 (:58)
- 6 - A 20 DFFE + 0 3 0 1 upl3 (:59)
- 1 - A 18 DFFE + 0 3 0 1 upl2 (:60)
- 8 - A 23 DFFE + 1 2 0 1 upl1 (:61)
- 7 - A 23 DFFE + 0 3 0 1 x (:62)
- 4 - A 13 DFFE + 0 3 1 9 mo (:63)
- 4 - A 15 DFFE + 1 1 0 1 downl3 (:64)
- 4 - A 18 DFFE + 0 4 0 1 downl2 (:65)
- 5 - A 20 DFFE + 0 0 0 1 downl1 (:66)
- 3 - A 21 DFFE + 0 3 0 1 y (:67)
- 4 - C 20 DFFE + 0 3 0 1 cnt231 (:68)
- 7 - C 23 DFFE + 0 3 0 2 cnt230 (:69)
- 5 - C 23 DFFE + 0 3 0 3 cnt229 (:70)
- 1 - C 23 DFFE + 0 3 0 4 cnt228 (:71)
- 6 - C 16 DFFE + 0 3 0 2 cnt227 (:72)
- 8 - C 16 DFFE + 0 3 0 3 cnt226 (:73)
- 3 - C 13 DFFE + 0 3 0 3 cnt225 (:74)
- 8 - C 24 DFFE + 0 3 0 2 cnt224 (:75)
- 6 - C 24 DFFE + 0 3 0 2 cnt223 (:76)
- 4 - C 13 DFFE + 0 3 0 2 cnt222 (:77)
- 8 - C 11 DFFE + 0 3 0 2 cnt221 (:78)
- 6 - C 11 DFFE + 0 3 0 2 cnt220 (:79)
- 1 - C 12 DFFE + 0 3 0 2 cnt219 (:80)
- 4 - C 10 DFFE + 0 3 0 2 cnt218 (:81)
- 3 - C 10 DFFE + 0 3 0 2 cnt217 (:82)
- 1 - C 08 DFFE + 0 3 0 2 cnt216 (:83)
- 3 - C 08 DFFE + 0 3 0 3 cnt215 (:84)
- 2 - C 08 DFFE + 0 3 0 4 cnt214 (:85)
- 8 - C 09 DFFE + 0 3 0 2 cnt213 (:86)
- 6 - C 09 DFFE + 0 3 0 2 cnt212 (:87)
- 2 - C 10 DFFE + 0 3 0 2 cnt211 (:88)
- 2 - C 19 DFFE + 0 3 0 2 cnt210 (:89)
- 8 - C 19 DFFE + 0 3 0 2 cnt29 (:90)
- 2 - C 13 DFFE + 0 3 0 2 cnt28 (:91)
- 2 - C 14 DFFE + 0 3 0 2 cnt27 (:92)
- 3 - C 14 DFFE + 0 3 0 2 cnt26 (:93)
- 1 - C 13 DFFE + 0 3 0 2 cnt25 (:94)
- 8 - C 15 DFFE + 0 3 0 2 cnt24 (:95)
- 6 - C 15 DFFE + 0 3 0 2 cnt23 (:96)
- 3 - C 17 DFFE + 0 3 0 2 cnt22 (:97)
- 8 - C 17 DFFE + 0 3 0 1 cnt21 (:98)
- 5 - C 17 DFFE + 0 3 0 3 cnt20 (:99)
- 7 - A 18 OR2 1 1 0 5 :280
- 3 - A 18 OR2 1 1 0 5 :344
- 6 - C 17 AND2 s 0 2 0 32 ~449~1
- 1 - A 13 AND2 s 0 3 0 1 ~449~2
- 2 - A 13 AND2 s 0 4 0 1 ~449~3
- 6 - A 23 AND2 s 0 4 0 1 ~449~4
- 1 - B 01 OR2 0 4 0 48 :449
- 2 - B 08 AND2 s 0 4 0 1 ~451~1
- 3 - B 05 OR2 s 0 4 0 1 ~451~2
- 2 - B 23 AND2 s 0 4 0 1 ~451~3
- 8 - B 19 AND2 s 0 4 0 1 ~451~4
- 3 - B 10 AND2 s 0 4 0 1 ~451~5
- 4 - B 11 AND2 s 0 4 0 1 ~451~6
- 2 - B 01 AND2 s 0 4 0 1 ~451~7
- 2 - B 12 AND2 s 0 4 0 1 ~451~8
- 3 - B 01 AND2 s 0 4 0 1 ~451~9
- 3 - A 20 OR2 0 4 0 5 :736
- 8 - A 18 OR2 1 2 0 7 :775
- 2 - A 20 OR2 0 4 0 2 :834
- 3 - A 23 AND2 ! 0 2 0 3 :1083
- 5 - A 18 OR2 1 2 0 7 :1265
- 2 - A 21 AND2 ! 0 2 0 2 :1269
- 7 - A 16 OR2 0 2 0 1 :1320
- 5 - A 16 OR2 0 4 0 1 :1416
- 2 - A 16 OR2 0 4 0 1 :1428
- 8 - A 16 OR2 0 4 0 1 :1434
- 4 - A 20 OR2 0 4 0 1 :1482
- 8 - A 20 OR2 s 0 4 0 1 ~1483~1
- 2 - A 15 AND2 ! 2 2 0 9 :1538
- 1 - A 23 OR2 2 2 0 9 :1544
- 6 - A 16 OR2 ! 0 3 0 2 :1587
- 3 - A 13 OR2 0 4 0 1 :1720
- 1 - C 20 OR2 0 4 0 3 :1759
- 2 - C 03 AND2 s 0 4 0 1 ~1761~1
- 2 - C 09 AND2 s 0 4 0 1 ~1761~2
- 4 - C 19 AND2 s 0 4 0 1 ~1761~3
- 2 - C 15 AND2 s 0 4 0 1 ~1761~4
- 1 - C 03 AND2 s 0 4 0 1 ~1761~5
- 2 - C 16 AND2 s 0 4 0 1 ~1761~6
- 2 - C 24 AND2 s 0 4 0 1 ~1761~7
- 2 - C 11 AND2 s 0 4 0 1 ~1761~8
- 2 - C 20 AND2 s 0 4 0 1 ~1761~9
- 1 - C 17 OR2 0 2 0 4 :1913
- 7 - A 24 AND2 0 3 0 1 :1962
- 2 - A 24 OR2 0 3 0 1 :2201
- 1 - A 24 OR2 s 0 3 0 1 ~2203~1
- 3 - A 16 OR2 0 3 0 1 :2207
- 6 - A 22 OR2 ! 0 2 0 38 :2216
- 5 - C 20 AND2 0 2 0 33 :2221
- 7 - A 22 AND2 0 2 0 7 :2224
- 3 - A 22 AND2 0 2 0 14 :2232
- 4 - A 24 OR2 0 4 0 1 :2289
- 6 - A 24 OR2 0 3 0 1 :2292
- 8 - A 24 OR2 0 3 0 1 :2295
- 4 - A 16 OR2 0 4 0 1 :2301
- 1 - A 16 OR2 0 3 0 1 :2304
- 1 - A 20 OR2 0 4 0 1 :2307
- 5 - A 13 OR2 0 3 0 1 :2397
- 8 - A 13 AND2 0 4 0 1 :2404
- 6 - A 13 OR2 0 4 0 1 :2405
- 7 - A 13 AND2 0 2 0 1 :2428
- 1 - A 19 OR2 s 0 4 0 1 ~2848~1
- 4 - A 22 OR2 s 0 2 0 1 ~2848~2
- 1 - A 17 OR2 s ! 0 3 0 35 ~3048~1
- 4 - A 23 AND2 s ! 0 2 0 1 ~3064~1
- 2 - A 17 OR2 s 0 3 0 4 ~3088~1
- 2 - A 23 OR2 s 0 3 0 1 ~3118~1
- 3 - A 15 OR2 s 0 3 0 2 ~3130~1
- 2 - A 18 OR2 s 0 2 0 1 ~3136~1
- 1 - A 21 OR2 s 0 2 0 1 ~3148~1
- 8 - C 23 OR2 s 0 4 0 2 ~3154~1
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