📄 veryhardd.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity veryhardd is
port(
up1,up2,down2,down3,clk,k1,k2,k3:in std_logic;
site:out std_logic_vector(3 downto 1);
a1,a2,a3:out std_logic;
mode,door:out std_logic);
end veryhardd;
architecture veryhardd_arc of veryhardd is
type state_type is(c1,c2,c3,kai);
begin
process(clk)
variable upl,downl,tingl,cengl:std_logic_vector(3 downto 1);
variable mo,x,y,z:std_logic;
variable cnt1,cnt2:integer;
variable state:state_type;
begin
if( clk'event and clk='1') then
if (up1='0' )then
upl(1):='1';
end if;
if (up2='0') then
upl(2):='1';
end if;
if( down3='0') then
downl(3):='1';
end if;
if(down2='0') then
downl(2):='1';
end if;
if (k1='0' )then
tingl(1):='1';
end if;
if (k2='0') then
tingl(2):='1';
end if;
if (k3='0' )then
tingl(3):='1';
end if;
if (cnt1<10 )then
cnt1:=cnt1+1;
else
case state is
when c1=>cengl:="001";
mo :='0';
if upl/="000"or downl/="000"or tingl/="000"then
z:='1';
end if;
if z='0' then
door<='1';
else
door<='0';
if tingl(1)='1' or upl(1)='1' then
state:=kai;
tingl(1):='0';
upl(1):='0';
elsif upl(2)='1' or tingl(2)='1' then
state:=c2;
elsif downl(3)='1' or tingl(3)='1' then
state:=c2;
x:='1';
elsif downl(2)='1' then
state:=c2;
mo:='1';
end if;
end if;
when c2=>cengl:="010";
if (mo='0' )then
if tingl(2)='1' or upl(2)='1' then
state:=kai;
tingl(2):='0';
upl(2):='0';
elsif (downl(3)='1' or tingl(3)='1' or x='1') then
state:=c3;
x:='0';
elsif (downl(2)='1' or upl(1)='1' or tingl(1)='1') then
mo:='1';
end if;
else
if( tingl(2)='1' or downl(2)='1' )then
state:=kai;
tingl(2):='0';
downl(2):='0';
elsif( upl(1)='1' or tingl(1)='1' or y='1') then
state:=c1;
y:='0';
elsif (upl(2) ='1' or downl(3)='1' or tingl(3)='1')then
mo:='0';
end if;
end if;
when c3=>mo:='1';
cengl:="100";
if (tingl(3)='1' or downl(3)='1' )then
state:=kai;
tingl(3):='0';
downl(3):='0';
elsif(downl(2)='1' or tingl(2)='1')then
state:=c2;
elsif (upl(1)='1' or tingl(1)='1') then
state:=c2;
y:='1';
elsif (upl(2)='1') then
state:=c2;
mo:='0';
end if;
when kai=>door<='1';
if (cnt2<3 )then
cnt2:=cnt2+1;
else
door<='0';
cnt2:=0;
if (cengl="001" )then
state:=c1;
elsif (cengl="010") then
state:=c2;
else
state:=c3;
end if;
end if;
end case;
cnt1:=0;
end if;
end if;
site<=cengl;
a1<=tingl(1);
a2<=tingl(2);
a3<=tingl(3);
mode<=mo;
end process;
end veryhardd_arc;
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