dian.rpt

这是一个用VHDL语言编写的电梯控制程序

  _EQ008 =  _LC2_A14 & !mode
         # !_LC1_A23 & !mode
         #  _LC1_A18;

-- Node name is ':17' 
-- Equation name is '_LC7_A20', type is buried 
_LC7_A20 = DFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 =  _LC5_A22 & !mode
         #  _LC1_A18;

-- Node name is ':19' 
-- Equation name is '_LC7_A18', type is buried 
_LC7_A18 = DFFE( _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 =  _LC3_A18
         #  _LC1_A18;

-- Node name is ':21' 
-- Equation name is '_LC4_A18', type is buried 
_LC4_A18 = DFFE( _EQ011, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 =  _LC3_A18
         #  _LC1_A18;

-- Node name is ':23' 
-- Equation name is '_LC6_A18', type is buried 
_LC6_A18 = DFFE( _EQ012, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ012 =  _LC3_A18
         #  _LC1_A18;

-- Node name is ':25' 
-- Equation name is '_LC8_A18', type is buried 
_LC8_A18 = DFFE( _EQ013, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ013 =  _LC3_A18
         #  _LC1_A18;

-- Node name is ':27' 
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = DFFE( _EQ014, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ014 =  _LC5_A22 &  mode
         #  _LC3_A18;

-- Node name is ':29' 
-- Equation name is '_LC8_A23', type is buried 
_LC8_A23 = DFFE( _EQ015, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ015 =  _LC2_A14 &  mode
         # !_LC1_A23 &  mode
         #  _LC3_A18;

-- Node name is ':31' 
-- Equation name is '_LC8_A20', type is buried 
_LC8_A20 = DFFE( _EQ016, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ016 =  _LC7_A22 &  mode
         #  _LC3_A18;

-- Node name is ':33' 
-- Equation name is '_LC6_A23', type is buried 
_LC6_A23 = DFFE( _EQ017, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ017 =  _LC3_A14 &  mode
         #  _LC3_A18;

-- Node name is ':35' 
-- Equation name is '_LC8_A14', type is buried 
_LC8_A14 = DFFE( _EQ018, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ018 =  _LC1_A14 &  _LC6_A14 &  mode
         #  _LC3_A18;

-- Node name is ':37' 
-- Equation name is '_LC5_A18', type is buried 
_LC5_A18 = DFFE( _EQ019, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ019 =  _LC3_A18
         #  _LC1_A18;

-- Node name is ':789' 
-- Equation name is '_LC7_A14', type is buried 
_LC7_A14 = LCELL( _EQ020);
  _EQ020 =  seel0 & !seel1 & !seel2 &  seel3;

-- Node name is ':828' 
-- Equation name is '_LC2_A22', type is buried 
_LC2_A22 = LCELL( _EQ021);
  _EQ021 =  seel1 &  seel2 & !seel3;

-- Node name is ':837' 
-- Equation name is '_LC3_A22', type is buried 
!_LC3_A22 = _LC3_A22~NOT;
_LC3_A22~NOT = LCELL( _EQ022);
  _EQ022 =  seel3
         # !seel2
         #  seel1
         # !seel0;

-- Node name is ':849' 
-- Equation name is '_LC5_A14', type is buried 
!_LC5_A14 = _LC5_A14~NOT;
_LC5_A14~NOT = LCELL( _EQ023);
  _EQ023 =  seel3
         # !seel2
         #  seel1
         #  seel0;

-- Node name is ':900' 
-- Equation name is '_LC6_A14', type is buried 
_LC6_A14 = LCELL( _EQ024);
  _EQ024 =  seel1 &  seel2 & !seel3
         #  seel0 &  seel2 & !seel3
         # !seel0 & !seel1 & !seel2 &  seel3;

-- Node name is ':995' 
-- Equation name is '_LC4_A22', type is buried 
_LC4_A22 = LCELL( _EQ025);
  _EQ025 =  seel1 & !seel2 &  seel3;

-- Node name is ':1007' 
-- Equation name is '_LC2_A14', type is buried 
_LC2_A14 = LCELL( _EQ026);
  _EQ026 = !_LC3_A22 &  _LC4_A22 & !_LC5_A14
         #  _LC2_A22 & !_LC3_A22 & !_LC5_A14;

-- Node name is ':1041' 
-- Equation name is '_LC5_A22', type is buried 
_LC5_A22 = LCELL( _EQ027);
  _EQ027 = !seel0 &  seel1 & !seel3
         #  seel1 &  seel2 & !seel3
         #  seel0 &  seel1 & !seel2 &  seel3;

-- Node name is ':2386' 
-- Equation name is '_LC3_A18', type is buried 
_LC3_A18 = LCELL( _EQ028);
  _EQ028 =  _LC1_A14 &  _LC2_A22 & !_LC3_A22 & !mode;

-- Node name is '~2387~1' 
-- Equation name is '~2387~1', location is LC1_A23, type is buried.
-- synthesized logic cell 
_LC1_A23 = LCELL( _EQ029);
  _EQ029 = !seel1
         #  seel2
         #  seel3;

-- Node name is '~2387~2' 
-- Equation name is '~2387~2', location is LC1_A14, type is buried.
-- synthesized logic cell 
_LC1_A14 = LCELL( _EQ030);
  _EQ030 =  _LC1_A23 & !_LC5_A14;

-- Node name is ':2387' 
-- Equation name is '_LC1_A18', type is buried 
_LC1_A18 = LCELL( _EQ031);
  _EQ031 =  _LC1_A14 &  _LC2_A22 & !_LC3_A22 &  mode;

-- Node name is '~2404~1' 
-- Equation name is '~2404~1', location is LC7_A22, type is buried.
-- synthesized logic cell 
_LC7_A22 = LCELL( _EQ032);
  _EQ032 = !seel0 &  seel2 & !seel3
         #  seel0 &  seel1 & !seel3
         #  seel0 & !seel1 & !seel2 &  seel3
         # !seel0 &  seel1 & !seel2 &  seel3;

-- Node name is '~2465~1' 
-- Equation name is '~2465~1', location is LC3_A14, type is buried.
-- synthesized logic cell 
_LC3_A14 = LCELL( _EQ033);
  _EQ033 =  _LC1_A23 &  _LC7_A14
         #  _LC1_A23 &  _LC6_A14
         #  _LC1_A23 &  _LC5_A14;



Project Information                                 e:\program\dianti\dian.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:02
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,831K