📄 dian.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\program\dianti\dian.rpt
dian
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 18 DFFE + 0 2 1 0 :7
- 4 - A 14 DFFE + 1 3 1 0 :9
- 5 - A 23 DFFE + 1 2 1 0 :11
- 1 - A 20 DFFE + 1 2 1 0 :13
- 3 - A 23 DFFE + 1 3 1 0 :15
- 7 - A 20 DFFE + 1 2 1 0 :17
- 7 - A 18 DFFE + 0 2 1 0 :19
- 4 - A 18 DFFE + 0 2 1 0 :21
- 6 - A 18 DFFE + 0 2 1 0 :23
- 8 - A 18 DFFE + 0 2 1 0 :25
- 2 - A 20 DFFE + 1 2 1 0 :27
- 8 - A 23 DFFE + 1 3 1 0 :29
- 8 - A 20 DFFE + 1 2 1 0 :31
- 6 - A 23 DFFE + 1 2 1 0 :33
- 8 - A 14 DFFE + 1 3 1 0 :35
- 5 - A 18 DFFE + 0 2 1 0 :37
- 6 - A 22 DFFE + 0 3 1 9 seel3 (:39)
- 8 - A 22 DFFE + 0 2 1 10 seel2 (:40)
- 1 - A 22 DFFE + 0 1 1 11 seel1 (:41)
- 3 - A 05 DFFE + 0 0 1 9 seel0 (:42)
- 7 - A 14 AND2 0 4 0 1 :789
- 2 - A 22 AND2 0 3 0 3 :828
- 3 - A 22 OR2 ! 0 4 0 3 :837
- 5 - A 14 OR2 ! 0 4 0 3 :849
- 6 - A 14 OR2 0 4 0 3 :900
- 4 - A 22 AND2 0 3 0 1 :995
- 2 - A 14 OR2 0 4 0 2 :1007
- 5 - A 22 OR2 0 4 0 2 :1041
- 3 - A 18 AND2 1 3 0 11 :2386
- 1 - A 23 OR2 s 0 3 0 4 ~2387~1
- 1 - A 14 AND2 s 0 2 0 4 ~2387~2
- 1 - A 18 AND2 1 3 0 11 :2387
- 7 - A 22 OR2 s 0 4 0 2 ~2404~1
- 3 - A 14 OR2 s 0 4 0 2 ~2465~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\program\dianti\dian.rpt
dian
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 1/ 48( 2%) 19/ 48( 39%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\program\dianti\dian.rpt
dian
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 clk
Device-Specific Information: e:\program\dianti\dian.rpt
dian
** EQUATIONS **
clk : INPUT;
mode : INPUT;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC2_A18;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC4_A14;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC5_A23;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC1_A20;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = _LC3_A23;
-- Node name is 'q5'
-- Equation name is 'q5', type is output
q5 = _LC7_A20;
-- Node name is 'q6'
-- Equation name is 'q6', type is output
q6 = _LC7_A18;
-- Node name is 'q7'
-- Equation name is 'q7', type is output
q7 = _LC4_A18;
-- Node name is 'q8'
-- Equation name is 'q8', type is output
q8 = _LC6_A18;
-- Node name is 'q9'
-- Equation name is 'q9', type is output
q9 = _LC8_A18;
-- Node name is 'q10'
-- Equation name is 'q10', type is output
q10 = _LC2_A20;
-- Node name is 'q11'
-- Equation name is 'q11', type is output
q11 = _LC8_A23;
-- Node name is 'q12'
-- Equation name is 'q12', type is output
q12 = _LC8_A20;
-- Node name is 'q13'
-- Equation name is 'q13', type is output
q13 = _LC6_A23;
-- Node name is 'q14'
-- Equation name is 'q14', type is output
q14 = _LC8_A14;
-- Node name is 'q15'
-- Equation name is 'q15', type is output
q15 = _LC5_A18;
-- Node name is ':42' = 'seel0'
-- Equation name is 'seel0', location is LC3_A5, type is buried.
seel0 = DFFE(!seel0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':41' = 'seel1'
-- Equation name is 'seel1', location is LC1_A22, type is buried.
seel1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !seel0 & seel1
# seel0 & !seel1;
-- Node name is ':40' = 'seel2'
-- Equation name is 'seel2', location is LC8_A22, type is buried.
seel2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !seel1 & seel2
# !seel0 & seel2
# seel0 & seel1 & !seel2;
-- Node name is ':39' = 'seel3'
-- Equation name is 'seel3', location is LC6_A22, type is buried.
seel3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !seel1 & seel3
# !seel0 & seel3
# !seel2 & seel3
# seel0 & seel1 & seel2 & !seel3;
-- Node name is 'sel0'
-- Equation name is 'sel0', type is output
sel0 = seel0;
-- Node name is 'sel1'
-- Equation name is 'sel1', type is output
sel1 = seel1;
-- Node name is 'sel2'
-- Equation name is 'sel2', type is output
sel2 = seel2;
-- Node name is 'sel3'
-- Equation name is 'sel3', type is output
sel3 = seel3;
-- Node name is ':7'
-- Equation name is '_LC2_A18', type is buried
_LC2_A18 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC3_A18
# _LC1_A18;
-- Node name is ':9'
-- Equation name is '_LC4_A14', type is buried
_LC4_A14 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC1_A14 & _LC6_A14 & !mode
# _LC1_A18;
-- Node name is ':11'
-- Equation name is '_LC5_A23', type is buried
_LC5_A23 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC3_A14 & !mode
# _LC1_A18;
-- Node name is ':13'
-- Equation name is '_LC1_A20', type is buried
_LC1_A20 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC7_A22 & !mode
# _LC1_A18;
-- Node name is ':15'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
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