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<br /><span class="tpc_content">3.信号转换模块――tolight.vhd<br>LIBRARY IEEE;<br>USE IEEE.STD_LOGIC_1164.ALL;<br>USE IEEE.STD_LOGIC_UNSIGNED.ALL;<br>ENTITY tolight IS<br> PORT ( clk2:IN STD_LOGIC;<br> statenum2:in STD_LOGIC_VECTOR(1 DOWNTO 0);<br> mr2,my2,mg2,cr2,cy2,cg2:OUT STD_LOGIC);<br>END tolight;<br>ARCHITECTURE behav OF tolight IS<br>begin<br> process(clk2)<br> begin<br> if clk2'event and clk2='1' then<br> case statenum2(1 downto 0) is<br> when "00"=>mr2<='0';my2<='0';mg2<='1';cr2<='1';cy2<='0';cg2<='0';<br> when "01"=>mr2<='0';my2<='1';mg2<='0';cr2<='1';cy2<='0';cg2<='0';<br> when "10"=>mr2<='1';my2<='0';mg2<='0';cr2<='0';cy2<='0';cg2<='1'; <br> when "11"=>mr2<='1';my2<='0';mg2<='0';cr2<='0';cy2<='1';cg2<='0';<br> when others=>mr2<='0';my2<='0';mg2<='1';cr2<='1';cy2<='0';cg2<='0';<br> end case;<br> end if;<br> end process;<br>end behav;<br><br>4.顶层文件――traffic.vhd<br>library ieee;<br>use ieee.std_logic_1164.all;<br>use ieee.std_logic_arith.all;<br>use ieee.std_logic_unsigned.all;<br>entity traffic is<br> port( clk:in std_logic;<br> s :in std_logic;<br> reset:in std_logic;<br> mr,my,mg,cr,cy,cg:OUT STD_LOGIC;<br> time:out std_logic_vector(7 downto 0));<br>end traffic;<br>ARCHITECTURE behav OF traffic IS<br>component controlm IS<br> PORT (clk0,reset0,s0,c0 :IN STD_LOGIC;<br> ld0 :out std_logic;<br> dinl0,dinh0 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);<br> state0 :OUT STD_LOGIC_VECTOR(1 DOWNTO 0));<br>END component controlm;<br>component mvc is<br> port( cp1:in std_logic;<br> ld1:in std_logic;<br> dinl1:in std_logic_vector(3 downto 0);<br> dinh1:in std_logic_vector(3 downto 0);<br> ql1:out std_logic_vector(3 downto 0);<br> qh1:out std_logic_vector(3 downto 0);<br> c1:out std_logic);<br>end component mvc;<br>component tolight IS<br> PORT ( clk2:IN STD_LOGIC;<br> statenum2:in STD_LOGIC_VECTOR(1 DOWNTO 0);<br> mr2,my2,mg2,cr2,cy2,cg2:OUT STD_LOGIC);<br>END component tolight;<br><br>signal c,ld :std_logic;<br>signal dinl,dinh:std_logic_vector(3 downto 0);<br>signal statenum :std_logic_vector(1 downto 0);<br>begin<br>u1: controlm port map(clk0=>clk,reset0=>reset,s0=>s,c0=>c,ld0=>ld,dinl0=>dinl,dinh0=>dinh,state0=>statenum);<br>u2: mvc port map(cp1=>clk,ld1=>ld,dinl1=>dinl,dinh1=>dinh,ql1=>time(3 downto 0),qh1=>time(7 downto 4),c1=>c);<br>u3: tolight port map(clk2=>clk,statenum2=>statenum,mr2=>mr,my2=>my,mg2=>mg,cr2=>cr,cy2=>cy,cg2=>cg);<br>end behav;<br><br>引脚锁定：<br>根据实验输入输出要求，选择模式五作为实验电路。<br>具体引脚锁定如下：<br>信号名 类型 使用电路信号 引脚<br>clk 输入 CLOCK0 126<br>s 输入 键8 19<br>reset 输入 键7 18<br>mr 输出 D8 19<br>my 输出 D7 28<br>mg 输出 D6 27<br>cr 输出 D5 26<br>cy 输出 D4 23<br>cg 输出 D3 22<br>time(7 downto 4) 输出 译码数码管8 96．95，92，91<br>time(3 downto 0) 输出 译码数码管7 90，89，88，87</span><br />
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