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<br /><span class="tpc_content"> 目的和要求：<br> 1．有MR(主红)、MY（主黄）、MG（主绿）、CR（乡红）、CY（乡黄）、CG（乡绿）六盏交通灯需要控制；<br> 2．交通灯由绿→红有4秒黄灯亮的间隔时间，由红→绿没有间隔时间；<br> 3．系统有MRCY、MRCG、MYCR、MGCR四个状态；<br> 4．相间公路右侧各埋有一个传感器，当有车辆通过相间公路时，发出请求信号S；<br> 5．平时系统停留在MGCR状态，一旦S信号有效，经MRCY转入MRCG状态，但要保证MRCG状态也不得短于一分钟；<br> 6．一旦S信号无效，系统脱离MRCG状态。随即经MRCY转入进入MGCR状态，计时S信号一直有效，MRCG状态也不得长于20秒钟。<br><br>实验仪器：GW/48系列EDA开发系统(包含EP1K30TC144-3)；<br>编程环境：MAXPLUS ii 10.2<br><br>VHDL程序： 分为三个底层文件和一个顶层文件：<br><br>1.控制模块――controlm.vhd<br>LIBRARY IEEE;<br>USE IEEE.STD_LOGIC_1164.ALL;<br>USE IEEE.STD_LOGIC_UNSIGNED.ALL;<br>ENTITY controlm IS<br> PORT (clk0,reset0,s0,c0 :IN STD_LOGIC;<br> ld0 :out std_logic;<br> dinl0,dinh0 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);<br> state0 :OUT STD_LOGIC_VECTOR(1 DOWNTO 0));<br>END controlm;<br>ARCHITECTURE behav OF controlm IS<br> signal statenum:std_logic_vector(1 downto 0);<br> signal ldt:std_logic;<br> signal reg:std_logic_vector(3 downto 0);<br>BEGIN<br>state0<=statenum;<br>ld0<=ldt;<br>reg<=statenum&s0&c0;<br>process(reg,clk0)<br> begin<br> if reset0='0' then<br> statenum<="00";dinh0<="0101";dinl0<="1001";ldt<='0'; <br> elsif clk0'event and clk0='0' then <br> case reg is<br> when "0100"|"0101"|"1101"|"1111"=> statenum<="00";dinh0<="0101";dinl0<="1001";ldt<='0';<br> when "1000"|"1001"|"1011" => statenum<="11";dinh0<="0000";dinl0<="0011";ldt<='0';<br> when "0011" => statenum<="01";dinh0<="0000";dinl0<="0011";ldt<='0';<br> when "0111" => statenum<="10";dinh0<="0001";dinl0<="1001";ldt<='0';<br> when others => ldt<='1';<br> end case;<br> end if;<br>end process;<br>end behav;<br><br>2.计数模块－－mvc.vhd<br>library ieee;<br>use ieee.std_logic_1164.all;<br>use ieee.std_logic_arith.all;<br>use ieee.std_logic_unsigned.all;<br>entity mvc is<br> port( cp1:in std_logic;<br> ld1:in std_logic;<br> dinl1:in std_logic_vector(3 downto 0);<br> dinh1:in std_logic_vector(3 downto 0);<br> ql1:out std_logic_vector(3 downto 0);<br> qh1:out std_logic_vector(3 downto 0);<br> c1:out std_logic);<br>end mvc;<br><br>architecture w of mvc is<br>signal qa,qat:std_logic_vector(3 downto 0);<br>signal qb,qbt:std_logic_vector(3 downto 0);<br>signal ca,cb :std_logic;<br><br>begin<br> qh1<=qb;<br> ql1<=qa;<br> process(cp1)<br> begin<br> qat<=dinl1;<br> if cp1'event and cp1='1' then<br> if ld1='0' then qa<=qat;ca<='0';<br> elsif(qa="0000" and qb="0000") then qa<="0000";<br> elsif(qa="0000") then qa<="1001";ca<='0';<br> elsif(qa="0001") then ca<='1';qa<="0000";<br> else qa<=qa-1;ca<='0';<br> end if;<br> end if;<br> end process;<br><br> process(ca,cp1)<br> begin<br> qbt<=dinh1;<br> if cp1'event and cp1='1' then<br> if ld1='0' then qb<=qbt;cb<='0';c1<='0';<br> elsif(qb="0000" and qa="0000") then qb<="0000";<br> elsif(qb="0000" and qa="0001") then c1<='1';<br> elsif(ca='1') then qb<=qb-1;<br> end if;<br> end if;<br> end process;<br>end w;</span><br />
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