📄 msp430x13x.h
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/********************************************************************
*
* Standard register and bit definitions for the Texas Instruments
* MSP430 microcontroller.
*
* This file supports assembler and C development for
* MSP430x13x devices.
*
* Texas Instruments, Version 1.6
*
* Rev. 1.2, Additional Timer B bit definitions.
* Renamed XTOFF to XT2OFF.
*
* Rev. 1.3, Removed leading 0 to aviod interpretation as octal
* values under C
* Included <In430.h> rather than "In430.h"
*
* Rev. 1.4, Corrected LPMx_EXIT to reference new intrinsic _BIC_SR_IRQ
* Changed TAIV and TBIV to be read-only
*
* Rev. 1.5, Enclose all #define statements with parentheses
*
* Rev. 1.6, Defined vectors for USART (in addition to UART)
*
********************************************************************/
#ifndef __msp430x13x
#define __msp430x13x
/************************************************************
* STANDARD BITS
************************************************************/
#define BIT0 (0x0001)
#define BIT1 (0x0002)
#define BIT2 (0x0004)
#define BIT3 (0x0008)
#define BIT4 (0x0010)
#define BIT5 (0x0020)
#define BIT6 (0x0040)
#define BIT7 (0x0080)
#define BIT8 (0x0100)
#define BIT9 (0x0200)
#define BITA (0x0400)
#define BITB (0x0800)
#define BITC (0x1000)
#define BITD (0x2000)
#define BITE (0x4000)
#define BITF (0x8000)
/************************************************************
* STATUS REGISTER BITS
************************************************************/
#define C (0x0001)
#define Z (0x0002)
#define N (0x0004)
#define V (0x0100)
#define GIE (0x0008)
#define CPUOFF (0x0010)
#define OSCOFF (0x0020)
#define SCG0 (0x0040)
#define SCG1 (0x0080)
/* Low Power Modes coded with Bits 4-7 in SR */
#ifndef __IAR_SYSTEMS_ICC /* Begin #defines for assembler */
#define LPM0 (CPUOFF)
#define LPM1 (SCG0+CPUOFF)
#define LPM2 (SCG1+CPUOFF)
#define LPM3 (SCG1+SCG0+CPUOFF)
#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
/* End #defines for assembler */
#else /* Begin #defines for C */
#define LPM0_bits (CPUOFF)
#define LPM1_bits (SCG0+CPUOFF)
#define LPM2_bits (SCG1+CPUOFF)
#define LPM3_bits (SCG1+SCG0+CPUOFF)
#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
#include <In430.h>
#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */
#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */
#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */
#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */
#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */
#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */
#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */
#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */
#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */
#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */
#endif /* End #defines for C */
/************************************************************
* PERIPHERAL FILE MAP
************************************************************/
/************************************************************
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
************************************************************/
#define IE1_ (0x0000) /* Interrupt Enable 1 */
sfrb IE1 = IE1_;
#define WDTIE (0x01)
#define OFIE (0x02)
#define NMIIE (0x10)
#define ACCVIE (0x20)
#define URXIE0 (0x40)
#define UTXIE0 (0x80)
#define IFG1_ (0x0002) /* Interrupt Flag 1 */
sfrb IFG1 = IFG1_;
#define WDTIFG (0x01)
#define OFIFG (0x02)
#define NMIIFG (0x10)
#define URXIFG0 (0x40)
#define UTXIFG0 (0x80)
#define ME1_ (0x0004) /* Module Enable 1 */
sfrb ME1 = ME1_;
#define URXE0 (0x40)
#define USPIE0 (0x40)
#define UTXE0 (0x80)
/************************************************************
* WATCHDOG TIMER
************************************************************/
#define WDTCTL_ (0x0120) /* Watchdog Timer Control */
sfrw WDTCTL = WDTCTL_;
/* The bit names have been prefixed with "WDT" */
#define WDTIS0 (0x0001)
#define WDTIS1 (0x0002)
#define WDTSSEL (0x0004)
#define WDTCNTCL (0x0008)
#define WDTTMSEL (0x0010)
#define WDTNMI (0x0020)
#define WDTNMIES (0x0040)
#define WDTHOLD (0x0080)
#define WDTPW (0x5A00)
/* WDT-interval times [1ms] coded with Bits 0-2 */
/* WDT is clocked by fMCLK (assumed 1MHz) */
#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */
#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */
#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
/* WDT is clocked by fACLK (assumed 32KHz) */
#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */
#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
/* Watchdog mode -> reset after expired time */
/* WDT is clocked by fMCLK (assumed 1MHz) */
#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */
#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */
#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
/* WDT is clocked by fACLK (assumed 32KHz) */
#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */
#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
/* INTERRUPT CONTROL */
/* These two bits are defined in the Special Function Registers */
/* #define WDTIE 0x01 */
/* #define WDTIFG 0x01 */
/************************************************************
* DIGITAL I/O Port1/2
************************************************************/
#define P1IN_ (0x0020) /* Port 1 Input */
const sfrb P1IN = P1IN_;
#define P1OUT_ (0x0021) /* Port 1 Output */
sfrb P1OUT = P1OUT_;
#define P1DIR_ (0x0022) /* Port 1 Direction */
sfrb P1DIR = P1DIR_;
#define P1IFG_ (0x0023) /* Port 1 Interrupt Flag */
sfrb P1IFG = P1IFG_;
#define P1IES_ (0x0024) /* Port 1 Interrupt Edge Select */
sfrb P1IES = P1IES_;
#define P1IE_ (0x0025) /* Port 1 Interrupt Enable */
sfrb P1IE = P1IE_;
#define P1SEL_ (0x0026) /* Port 1 Selection */
sfrb P1SEL = P1SEL_;
#define P2IN_ (0x0028) /* Port 2 Input */
const sfrb P2IN = P2IN_;
#define P2OUT_ (0x0029) /* Port 2 Output */
sfrb P2OUT = P2OUT_;
#define P2DIR_ (0x002A) /* Port 2 Direction */
sfrb P2DIR = P2DIR_;
#define P2IFG_ (0x002B) /* Port 2 Interrupt Flag */
sfrb P2IFG = P2IFG_;
#define P2IES_ (0x002C) /* Port 2 Interrupt Edge Select */
sfrb P2IES = P2IES_;
#define P2IE_ (0x002D) /* Port 2 Interrupt Enable */
sfrb P2IE = P2IE_;
#define P2SEL_ (0x002E) /* Port 2 Selection */
sfrb P2SEL = P2SEL_;
/************************************************************
* DIGITAL I/O Port3/4
************************************************************/
#define P3IN_ (0x0018) /* Port 3 Input */
const sfrb P3IN = P3IN_;
#define P3OUT_ (0x0019) /* Port 3 Output */
sfrb P3OUT = P3OUT_;
#define P3DIR_ (0x001A) /* Port 3 Direction */
sfrb P3DIR = P3DIR_;
#define P3SEL_ (0x001B) /* Port 3 Selection */
sfrb P3SEL = P3SEL_;
#define P4IN_ (0x001C) /* Port 4 Input */
const sfrb P4IN = P4IN_;
#define P4OUT_ (0x001D) /* Port 4 Output */
sfrb P4OUT = P4OUT_;
#define P4DIR_ (0x001E) /* Port 4 Direction */
sfrb P4DIR = P4DIR_;
#define P4SEL_ (0x001F) /* Port 4 Selection */
sfrb P4SEL = P4SEL_;
/************************************************************
* DIGITAL I/O Port5/6
************************************************************/
#define P5IN_ (0x0030) /* Port 5 Input */
const sfrb P5IN = P5IN_;
#define P5OUT_ (0x0031) /* Port 5 Output */
sfrb P5OUT = P5OUT_;
#define P5DIR_ (0x0032) /* Port 5 Direction */
sfrb P5DIR = P5DIR_;
#define P5SEL_ (0x0033) /* Port 5 Selection */
sfrb P5SEL = P5SEL_;
#define P6IN_ (0x0034) /* Port 6 Input */
const sfrb P6IN = P6IN_;
#define P6OUT_ (0x0035) /* Port 6 Output */
sfrb P6OUT = P6OUT_;
#define P6DIR_ (0x0036) /* Port 6 Direction */
sfrb P6DIR = P6DIR_;
#define P6SEL_ (0x0037) /* Port 6 Selection */
sfrb P6SEL = P6SEL_;
/************************************************************
* USART
************************************************************/
#define PENA (0x80) /* UCTL */
#define PEV (0x40)
#define SPB (0x20) /* to distinguish from stackpointer SP */
#define CHAR (0x10)
#define LISTEN (0x08)
#define SYNC (0x04)
#define MM (0x02)
#define SWRST (0x01)
#define CKPH (0x80) /* UTCTL */
#define CKPL (0x40)
#define SSEL1 (0x20)
#define SSEL0 (0x10)
#define URXSE (0x08)
#define TXWAKE (0x04)
#define STC (0x02)
#define TXEPT (0x01)
#define FE (0x80) /* URCTL */
#define PE (0x40)
#define OE (0x20)
#define BRK (0x10)
#define URXEIE (0x08)
#define URXWIE (0x04)
#define RXWAKE (0x02)
#define RXERR (0x01)
/************************************************************
* USART 0
************************************************************/
#define U0CTL_ (0x0070) /* USART 0 Control */
sfrb U0CTL = U0CTL_;
#define U0TCTL_ (0x0071) /* USART 0 Transmit Control */
sfrb U0TCTL = U0TCTL_;
#define U0RCTL_ (0x0072) /* USART 0 Receive Control */
sfrb U0RCTL = U0RCTL_;
#define U0MCTL_ (0x0073) /* USART 0 Modulation Control */
sfrb U0MCTL = U0MCTL_;
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