adcdac.c

基于MST-G240128点阵液晶的 状态机机制 人机界面四级滚屏菜单 源代码 ,带时间片机制模拟操作系统

   ADC0_GAIN_Setting(0x00);      // ADC0 GAIN: 1. 
   uiTMP = 0;
   for(i=0;i<101;i++)
   {
      AD0INT = 0;                             // RST ADC Convert Complete Flag.
      AD0BUSY = 1;                            // Start ADC0    
      while( AD0INT == 0 );                   // Wait for Convert Over
      if( i>0 )
	  {
	  	 uiTMP = uiTMP + ADC0H * 256;
	     uiTMP = uiTMP + ADC0L;
 	  }
   }
   uiTMP = uiTMP / 100;
   return (unsigned char)uiTMP; 
}

/****************************************************************************
** 函数名称: ADC2_Init()
** 功能描述: 初始化CAN控制器定时、波特率，使能CAN控制器
** 入口参数: ADC2_EN:    0,ADC2 Disabled; 1,ADC2 Enabled; 
             ADC2_Mode:  0,AD2BUSY; 1,T3; 2,CNVSTR; 3,T2; >=4,AD0BUSY.
             ADC2_ChNum: The Channal to ADC.
             ADC2_GAIN:  GAIN of ADC2: 00(0),0.5; 01(1),1; 10(2),2; 11(3),4.
** 出口参数: 无
** 全局变量: 无
** 调用模块: 无
** 说明: 
****************************************************************************/
void ADC2_Init(bit ADC2_EN,unsigned char ADC2_Mode,unsigned char ADC2_ChNum,unsigned char ADC2_GAIN)
{
    unsigned char ucTMP;
	SFRPAGE = ADC2_PAGE;    // Switch to ADC2 Page
	AMX2CF = 0x00;          // All Channals are Single-Ended input
//	AMX2CF(00000000): AMUX2 Configuration Register.
//  Bits7-4: UNUSED. Read = 0000b; Write = don’t care
//	Bit3: PIN67IC: P1.6, P1.7 Input Pair Configuration Bit
//	      0/1: P1.6 and P1.7 are single-ended / differential input pair
//	Bit2: PIN45IC: P1.4, P1.5 Input Pair Configuration Bit
//	      0/1: P1.4 and P1.5 are single-ended / differential input pair
//	Bit1: PIN23IC: P1.2, P1.3 Input Pair Configuration Bit
//	      0/1: P1.2 and P1.3 are single-ended / differential input pair
//	Bit0: PIN01IC: P1.0, P1.1 Input Pair Configuration Bit
//	      0/1: P1.0 and P1.1 are single-ended / differential input pair
    AMX2SL = ADC2_ChNum;    // Channal AIN2.0.
//  AMX2SL(00000000): AMUX2 Channel Select Register.
//  Bits7-3: UNUSED. Read = 00000b; Write = don't care.
//  Bits2-0: AMX2AD2-0: AMX2 Address Bits.
	ADC2CF = 0x48 | ADC2_GAIN; 	// 1000 10xx Use the 2.5M SAR CLOCK ( <=250k SPS ).
//  ADC2CF(00000000): ADC2 Configuration Register.
//  Bits7-3: AD2SC4-0: ADC2 SAR Conversion Clock Period Bits.
//           AD2SC[4..0] = (SYSCLK/ADC2_SAR_CLK)-1. SYSCLK: 24.000MHz.
//  Bit2: UNUSED. Read = 0b. Write = don’t care.
//  Bits1-0: AMP2GN1-0: ADC2 Internal Amplifier Gain (PGA).
//		      00   01  10  11  
//     GAIN:  0.5  1   2   4    
    if( ADC2_EN == 1 )
      ADC2CN = 0x80;               // ADC2 Enabled.
    else
	  ADC2CN = 0x00;               // ADC2 Disabled.
    ucTMP = ADC2_Mode;
    ucTMP = (ucTMP << 1) & 0x0e;   // Only Bit[3..1](Periours Bit[2..0]) is Valid.  
	ADC2CN = ADC2CN | ucTMP;       // 1000 | ucTMP[4..0].   
//	ADC2CN(00000000): ADC2 Control Register.
//  Bit7: AD2EN: ADC2 Enable Bit.
//        0/1: ADC2 Disabled / Enabled. 
//	Bit6: AD2TM: ADC2 Track Mode Bit.
//	      0/1: Normal Track Mode / Low-power Track Mode.
//	Bit5: AD2INT: ADC2 Conversion Complete Interrupt Flag,and Cleared by software.
//	      0/1: ADC2 has Not Completed / Completed a data conversion.
//	Bit4: AD2BUSY: ADC2 Busy Bit.
//		  Read: 0/1: ADC2 Conversion is complete / ADC2 Conversion is in progress.
//        Write:0/1: No Effect / InitiatesADC2 Conversion if AD2STM2-0 = 000b
//	Bits3-1: AD2CM2-0: ADC2 Start of Conversion Mode Select.
//		  AD2TM = 0:
//			  000: ADC2 conversion initiated on every write of ‘1’ to AD2BUSY.
//			  001: ADC2 conversion initiated on overflow of Timer 3.
//			  010: ADC2 conversion initiated on rising edge of external CNVSTR2 or CNVSTR0.
//			  011: ADC2 conversion initiated on overflow of Timer 2.
//			  1xx: ADC2 conversion initiated on write of ‘1’ to AD0BUSY (synchronized with ADC0 softwarecommanded conversions).
//		  AD2TM = 1:
//			  000: Tracking initiated on write of ‘1’ to AD2BUSY and lasts 3 SAR2 clocks, followed by conversion.
//			  001: Tracking initiated on overflow of Timer 3 and lasts 3 SAR2 clocks, followed by conversion.
//			  010: ADC2 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge.
//			  011: Tracking initiated on overflow of Timer 2 and lasts 3 SAR2 clocks, followed by conversion.
//			  1xx: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR2 clocks, followed by conversion.
// 	Bit0: AD2WINT: ADC2 Window Compare Interrupt Flag.
//	      0/1: ADC2 window comparison data match has Not Occurred / Occurred. 
//  ADC2:   ADC2 Data Word Register.
//  ADC2GT: ADC2 Greater-Than Data Register.
//  ADC2LT: ADC2 Less-Than Data Register.
}

/****************************************************************************
** 函数名称: ADC2_CH_Setting()
** 功能描述: ADC2采样通道设置.
** 入口参数: ADC2_ChNum: The Channal to ADC.
** 出口参数: 无
** 全局变量: 无
** 调用模块: 无
** 说明: 
****************************************************************************/
void ADC2_CH_Setting(unsigned char ADC2_ChNum)
{
	SFRPAGE = ADC2_PAGE;         // Switch to ADC2 page.
	AMX2SL = ADC2_ChNum;
}

/****************************************************************************
** 函数名称: ADC2_Mode_Setting()
** 功能描述: ADC2工作模式设置.
** 入口参数: ADC2_Mode:  0,AD2BUSY; 1,T3; 2,CNVSTR; 3,T2.
** 出口参数: 无
** 全局变量: 无
** 调用模块: 无
** 说明: 
****************************************************************************/
void ADC2_Mode_Setting(unsigned char ADC2_Mode)
{
    unsigned char ucTMP;
	SFRPAGE = ADC2_PAGE;         // Switch to ADC2 page.
    ucTMP = ADC2_Mode;
    ucTMP = (ucTMP << 1) & 0x0e; // Only Bit[3..1](Periours Bit[2..0]) is Valid.  
	ADC2CN = 0x80 | ucTMP;       // 1000 | ucTMP[4..0].   
}

/****************************************************************************
** 函数名称: ADC2_GAIN_Setting()
** 功能描述: ADC2输入PGA放大倍数设置.
** 入口参数: ADC2_GAIN：GAIN of ADC2: 00,0.5; 01,1; 10,2; 11,4;
** 出口参数: 无
** 全局变量: 无
** 调用模块: 无
** 说明: 
****************************************************************************/
void ADC2_GAIN_Setting(unsigned char ADC2_GAIN)
{
	SFRPAGE = ADC2_PAGE;         // Switch to ADC2 page.
	ADC2CF = 0x48 | ADC2_GAIN; 	 // 1000 10xx Use the 2.5M SAR CLOCK ( <=250k SPS ).
}

/****************************************************************************
** 函数名称: DAC0_Init()
** 功能描述: C8051F040的DAC0的使能、工作模式和数据对齐格式初始化.
** 入口参数: DAC0_EN：  DAC0使能.
**           DAC0_Mode：DAC0数据更新模式.
**           DAC0_LJST: DAC0数据对齐格式.
** 出口参数: 无
** 全局变量: 无
** 调用模块: 无
** 说明: 
****************************************************************************/
void DAC0_Init(bit DAC0_EN,unsigned char DAC0_Mode,unsigned char DAC0_LJST)
{
   unsigned char ucTMP;
   SFRPAGE = DAC0_PAGE;          // Switch to DAC0 Page
   if( DAC0_EN )                 // DAC0 Enabled. 
     DAC0CN = 0x80;  
   ucTMP = DAC0_Mode;
   ucTMP = ucTMP << 3;
   DAC0CN = DAC0CN | ucTMP;      // DAC0 DATA Refresh Mode.
   DAC0CN = DAC0CN | DAC0_LJST;  // DAC0 DATA Right/Left-Justified. 
   // DAC0CN(00000000): DAC0 Control Register
   // Bit7: DAC0EN: 0/1 DAC0 Disabled/Enabled.
   // Bits4-3: DAC0MD1-0: DAC0 Mode Bits.
   //          00: DAC output updates occur on a write to DAC0H.
   //          01: DAC output updates occur on Timer 3 overflow.
   //          10: DAC output updates occur on Timer 4 overflow.
   //          11: DAC output updates occur on Timer 2 overflow.
   // Bits2-0: DAC0DF2-0: DAC0 Data Format Bits.
   //          000/111: Right/Left Justified. 
   // DAC0H: DAC0 High Byte Register
   // DAC0L: DAC0 Low  Byte Register
}

/****************************************************************************
** 函数名称: DAC1_Init()
** 功能描述: C8051F040的DAC1的使能、工作模式和数据对齐格式初始化.
** 入口参数: DAC1_EN：  DAC1使能.
**           DAC1_Mode：DAC1数据更新模式.
**           DAC1_LJST: DAC1数据对齐格式.
** 出口参数: 无
** 全局变量: 无
** 调用模块: 无
** 说明: 
****************************************************************************/
void DAC1_Init(bit DAC1_EN,unsigned char DAC1_Mode,unsigned char DAC1_LJST)
{
   unsigned char ucTMP;
   SFRPAGE = DAC1_PAGE;          // Switch to DAC1 Page   
   if( DAC1_EN )                 // DAC1 Enabled. 
     DAC1CN = 0x80;  
   ucTMP = DAC1_Mode;
   ucTMP = ucTMP << 3;
   DAC1CN = DAC1CN | ucTMP;      // DAC1 DATA Refresh Mode.
   DAC1CN = DAC1CN | DAC1_LJST;  // DAC1 DATA Right/Left-Justified. 
   // DAC1CN(00000000): DAC1 Control Register
   // Bit7: DAC1EN: 0/1 DAC1 Disabled/Enabled.
   // Bits4-3: DAC1MD1-0: DAC1 Mode Bits.
   //          00: DAC output updates occur on a write to DAC1H.
   //          01: DAC output updates occur on Timer 3 overflow.
   //          10: DAC output updates occur on Timer 4 overflow.
   //          11: DAC output updates occur on Timer 2 overflow.
   // Bits2-0: DAC1DF2-0: DAC1 Data Format Bits.
   //          000/111: Right/Left Justified. 
   // DAC1H: DAC1 High Byte Register
   // DAC1L: DAC1 Low  Byte Register
}