📄 adcdac.lst
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215 2 AD0BUSY = 1; // Start ADC0
216 2 while( AD0INT == 0 ); // Wait for Convert Over
217 2 if( i>0 )
218 2 {
219 3 uiTMP = uiTMP + ADC0H * 256;
220 3 uiTMP = uiTMP + ADC0L;
221 3 }
222 2 }
223 1 uiTMP = uiTMP / 100;
224 1 return (unsigned char)uiTMP;
225 1 }
226
227 /****************************************************************************
228 ** 函数名称: ADC2_Init()
229 ** 功能描述: 初始化CAN控制器定时、波特率，使能CAN控制器
230 ** 入口参数: ADC2_EN: 0,ADC2 Disabled; 1,ADC2 Enabled;
231 ADC2_Mode: 0,AD2BUSY; 1,T3; 2,CNVSTR; 3,T2; >=4,AD0BUSY.
232 ADC2_ChNum: The Channal to ADC.
233 ADC2_GAIN: GAIN of ADC2: 00(0),0.5; 01(1),1; 10(2),2; 11(3),4.
234 ** 出口参数: 无
235 ** 全局变量: 无
236 ** 调用模块: 无
237 ** 说明:
238 ****************************************************************************/
239 void ADC2_Init(bit ADC2_EN,unsigned char ADC2_Mode,unsigned char ADC2_ChNum,unsigned char ADC2_GAIN)
240 {
C51 COMPILER V7.20 ADCDAC 01/31/2007 10:20:44 PAGE 5
241 1 unsigned char ucTMP;
242 1 SFRPAGE = ADC2_PAGE; // Switch to ADC2 Page
243 1 AMX2CF = 0x00; // All Channals are Single-Ended input
244 1 // AMX2CF(00000000): AMUX2 Configuration Register.
245 1 // Bits7-4: UNUSED. Read = 0000b; Write = don’t care
246 1 // Bit3: PIN67IC: P1.6, P1.7 Input Pair Configuration Bit
247 1 // 0/1: P1.6 and P1.7 are single-ended / differential input pair
248 1 // Bit2: PIN45IC: P1.4, P1.5 Input Pair Configuration Bit
249 1 // 0/1: P1.4 and P1.5 are single-ended / differential input pair
250 1 // Bit1: PIN23IC: P1.2, P1.3 Input Pair Configuration Bit
251 1 // 0/1: P1.2 and P1.3 are single-ended / differential input pair
252 1 // Bit0: PIN01IC: P1.0, P1.1 Input Pair Configuration Bit
253 1 // 0/1: P1.0 and P1.1 are single-ended / differential input pair
254 1 AMX2SL = ADC2_ChNum; // Channal AIN2.0.
255 1 // AMX2SL(00000000): AMUX2 Channel Select Register.
256 1 // Bits7-3: UNUSED. Read = 00000b; Write = don't care.
257 1 // Bits2-0: AMX2AD2-0: AMX2 Address Bits.
258 1 ADC2CF = 0x48 | ADC2_GAIN; // 1000 10xx Use the 2.5M SAR CLOCK ( <=250k SPS ).
259 1 // ADC2CF(00000000): ADC2 Configuration Register.
260 1 // Bits7-3: AD2SC4-0: ADC2 SAR Conversion Clock Period Bits.
261 1 // AD2SC[4..0] = (SYSCLK/ADC2_SAR_CLK)-1. SYSCLK: 24.000MHz.
262 1 // Bit2: UNUSED. Read = 0b. Write = don’t care.
263 1 // Bits1-0: AMP2GN1-0: ADC2 Internal Amplifier Gain (PGA).
264 1 // 00 01 10 11
265 1 // GAIN: 0.5 1 2 4
266 1 if( ADC2_EN == 1 )
267 1 ADC2CN = 0x80; // ADC2 Enabled.
268 1 else
269 1 ADC2CN = 0x00; // ADC2 Disabled.
270 1 ucTMP = ADC2_Mode;
271 1 ucTMP = (ucTMP << 1) & 0x0e; // Only Bit[3..1](Periours Bit[2..0]) is Valid.
272 1 ADC2CN = ADC2CN | ucTMP; // 1000 | ucTMP[4..0].
273 1 // ADC2CN(00000000): ADC2 Control Register.
274 1 // Bit7: AD2EN: ADC2 Enable Bit.
275 1 // 0/1: ADC2 Disabled / Enabled.
276 1 // Bit6: AD2TM: ADC2 Track Mode Bit.
277 1 // 0/1: Normal Track Mode / Low-power Track Mode.
278 1 // Bit5: AD2INT: ADC2 Conversion Complete Interrupt Flag,and Cleared by software.
279 1 // 0/1: ADC2 has Not Completed / Completed a data conversion.
280 1 // Bit4: AD2BUSY: ADC2 Busy Bit.
281 1 // Read: 0/1: ADC2 Conversion is complete / ADC2 Conversion is in progress.
282 1 // Write:0/1: No Effect / InitiatesADC2 Conversion if AD2STM2-0 = 000b
283 1 // Bits3-1: AD2CM2-0: ADC2 Start of Conversion Mode Select.
284 1 // AD2TM = 0:
285 1 // 000: ADC2 conversion initiated on every write of ‘1’ to AD2BUSY.
286 1 // 001: ADC2 conversion initiated on overflow of Timer 3.
287 1 // 010: ADC2 conversion initiated on rising edge of external CNVSTR2 or CNVSTR0.
288 1 // 011: ADC2 conversion initiated on overflow of Timer 2.
289 1 // 1xx: ADC2 conversion initiated on write of ‘1’ to AD0BUSY (synchronized with ADC0 softwarecommand
-ed conversions).
290 1 // AD2TM = 1:
291 1 // 000: Tracking initiated on write of ‘1’ to AD2BUSY and lasts 3 SAR2 clocks, followed by conversio
-n.
292 1 // 001: Tracking initiated on overflow of Timer 3 and lasts 3 SAR2 clocks, followed by conversion.
293 1 // 010: ADC2 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge.
294 1 // 011: Tracking initiated on overflow of Timer 2 and lasts 3 SAR2 clocks, followed by conversion.
295 1 // 1xx: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR2 clocks, followed by conversio
-n.
296 1 // Bit0: AD2WINT: ADC2 Window Compare Interrupt Flag.
297 1 // 0/1: ADC2 window comparison data match has Not Occurred / Occurred.
298 1 // ADC2: ADC2 Data Word Register.
299 1 // ADC2GT: ADC2 Greater-Than Data Register.
C51 COMPILER V7.20 ADCDAC 01/31/2007 10:20:44 PAGE 6
300 1 // ADC2LT: ADC2 Less-Than Data Register.
301 1 }
302
303 /****************************************************************************
304 ** 函数名称: ADC2_CH_Setting()
305 ** 功能描述: ADC2采样通道设置.
306 ** 入口参数: ADC2_ChNum: The Channal to ADC.
307 ** 出口参数: 无
308 ** 全局变量: 无
309 ** 调用模块: 无
310 ** 说明:
311 ****************************************************************************/
312 void ADC2_CH_Setting(unsigned char ADC2_ChNum)
313 {
314 1 SFRPAGE = ADC2_PAGE; // Switch to ADC2 page.
315 1 AMX2SL = ADC2_ChNum;
316 1 }
317
318 /****************************************************************************
319 ** 函数名称: ADC2_Mode_Setting()
320 ** 功能描述: ADC2工作模式设置.
321 ** 入口参数: ADC2_Mode: 0,AD2BUSY; 1,T3; 2,CNVSTR; 3,T2.
322 ** 出口参数: 无
323 ** 全局变量: 无
324 ** 调用模块: 无
325 ** 说明:
326 ****************************************************************************/
327 void ADC2_Mode_Setting(unsigned char ADC2_Mode)
328 {
329 1 unsigned char ucTMP;
330 1 SFRPAGE = ADC2_PAGE; // Switch to ADC2 page.
331 1 ucTMP = ADC2_Mode;
332 1 ucTMP = (ucTMP << 1) & 0x0e; // Only Bit[3..1](Periours Bit[2..0]) is Valid.
333 1 ADC2CN = 0x80 | ucTMP; // 1000 | ucTMP[4..0].
334 1 }
335
336 /****************************************************************************
337 ** 函数名称: ADC2_GAIN_Setting()
338 ** 功能描述: ADC2输入PGA放大倍数设置.
339 ** 入口参数: ADC2_GAIN：GAIN of ADC2: 00,0.5; 01,1; 10,2; 11,4;
340 ** 出口参数: 无
341 ** 全局变量: 无
342 ** 调用模块: 无
343 ** 说明:
344 ****************************************************************************/
345 void ADC2_GAIN_Setting(unsigned char ADC2_GAIN)
346 {
347 1 SFRPAGE = ADC2_PAGE; // Switch to ADC2 page.
348 1 ADC2CF = 0x48 | ADC2_GAIN; // 1000 10xx Use the 2.5M SAR CLOCK ( <=250k SPS ).
349 1 }
350
351 /****************************************************************************
352 ** 函数名称: DAC0_Init()
353 ** 功能描述: C8051F040的DAC0的使能、工作模式和数据对齐格式初始化.
354 ** 入口参数: DAC0_EN： DAC0使能.
355 ** DAC0_Mode：DAC0数据更新模式.
356 ** DAC0_LJST: DAC0数据对齐格式.
357 ** 出口参数: 无
358 ** 全局变量: 无
359 ** 调用模块: 无
360 ** 说明:
361 ****************************************************************************/
C51 COMPILER V7.20 ADCDAC 01/31/2007 10:20:44 PAGE 7
362 void DAC0_Init(bit DAC0_EN,unsigned char DAC0_Mode,unsigned char DAC0_LJST)
363 {
364 1 unsigned char ucTMP;
365 1 SFRPAGE = DAC0_PAGE; // Switch to DAC0 Page
366 1 if( DAC0_EN ) // DAC0 Enabled.
367 1 DAC0CN = 0x80;
368 1 ucTMP = DAC0_Mode;
369 1 ucTMP = ucTMP << 3;
370 1 DAC0CN = DAC0CN | ucTMP; // DAC0 DATA Refresh Mode.
371 1 DAC0CN = DAC0CN | DAC0_LJST; // DAC0 DATA Right/Left-Justified.
372 1 // DAC0CN(00000000): DAC0 Control Register
373 1 // Bit7: DAC0EN: 0/1 DAC0 Disabled/Enabled.
374 1 // Bits4-3: DAC0MD1-0: DAC0 Mode Bits.
375 1 // 00: DAC output updates occur on a write to DAC0H.
376 1 // 01: DAC output updates occur on Timer 3 overflow.
377 1 // 10: DAC output updates occur on Timer 4 overflow.
378 1 // 11: DAC output updates occur on Timer 2 overflow.
379 1 // Bits2-0: DAC0DF2-0: DAC0 Data Format Bits.
380 1 // 000/111: Right/Left Justified.
381 1 // DAC0H: DAC0 High Byte Register
382 1 // DAC0L: DAC0 Low Byte Register
383 1 }
384
385 /****************************************************************************
386 ** 函数名称: DAC1_Init()
387 ** 功能描述: C8051F040的DAC1的使能、工作模式和数据对齐格式初始化.
388 ** 入口参数: DAC1_EN： DAC1使能.
389 ** DAC1_Mode：DAC1数据更新模式.
390 ** DAC1_LJST: DAC1数据对齐格式.
391 ** 出口参数: 无
392 ** 全局变量: 无
393 ** 调用模块: 无
394 ** 说明:
395 ****************************************************************************/
396 void DAC1_Init(bit DAC1_EN,unsigned char DAC1_Mode,unsigned char DAC1_LJST)
397 {
398 1 unsigned char ucTMP;
399 1 SFRPAGE = DAC1_PAGE; // Switch to DAC1 Page
400 1 if( DAC1_EN ) // DAC1 Enabled.
401 1 DAC1CN = 0x80;
402 1 ucTMP = DAC1_Mode;
403 1 ucTMP = ucTMP << 3;
404 1 DAC1CN = DAC1CN | ucTMP; // DAC1 DATA Refresh Mode.
405 1 DAC1CN = DAC1CN | DAC1_LJST; // DAC1 DATA Right/Left-Justified.
406 1 // DAC1CN(00000000): DAC1 Control Register
407 1 // Bit7: DAC1EN: 0/1 DAC1 Disabled/Enabled.
408 1 // Bits4-3: DAC1MD1-0: DAC1 Mode Bits.
409 1 // 00: DAC output updates occur on a write to DAC1H.
410 1 // 01: DAC output updates occur on Timer 3 overflow.
411 1 // 10: DAC output updates occur on Timer 4 overflow.
412 1 // 11: DAC output updates occur on Timer 2 overflow.
413 1 // Bits2-0: DAC1DF2-0: DAC1 Data Format Bits.
414 1 // 000/111: Right/Left Justified.
415 1 // DAC1H: DAC1 High Byte Register
416 1 // DAC1L: DAC1 Low Byte Register
417 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 284 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
C51 COMPILER V7.20 ADCDAC 01/31/2007 10:20:44 PAGE 8
PDATA SIZE = ---- ----
DATA SIZE = ---- 11
IDATA SIZE = ---- ----
BIT SIZE = ---- 7
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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