can.h

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#ifndef  CAN_H
#define  CAN_H


extern uint8 xdata CAN_SendDATA[8];
extern uint8 xdata CAN_RecvDATA[8];


#define CAN_6CLK   1             // 1(uS)   

// sfr  CAN0CN   = 0xF8;         /* CAN 0 CONTROL            */	
// sbit CANTEST  = CAN0CN ^ 7;   /* CAN Test Mode Enable bit */
// sbit CANCCE   = CAN0CN ^ 6;   /* CAN Configuration Change Enable bit */
// sbit CANDAR   = CAN0CN ^ 5;   /* CAN Disable Automatic Retransmission bit */
// sbit CANIF    = CAN0CN ^ 4;   /* CAN Module Interrupt Flag */
// sbit CANEIE   = CAN0CN ^ 3;   /* CAN Module Error Interrupt Enable Bit */
// sbit CANSIE   = CAN0CN ^ 2;   /* CAN Status change Interrupt Enable Bit */
// sbit CANIE    = CAN0CN ^ 1;   /* CAN Module Interrupt Enable Bit */
// sbit CANINIT  = CAN0CN ^ 0;   /* CAN Initialization bit */

// sfr  CAN0ADR  = 0xDA;        /* CAN 0 ADDRESS                   */
// sfr  CAN0DATH = 0xD9;        /* CAN 0 DATA - HIGH BYTE          */
// sfr  CAN0DATL = 0xD8;        /* CAN 0 DATA - LOW BYTE           */

sfr16 CAN0DAT = 0xD8;

// sfr  CAN0STA  = 0xC0;          /* CAN 0 STATUS                    */
// sbit BOFF     = CAN0STA ^ 7;   /* Bus Off Status                  */
// sbit EWARN    = CAN0STA ^ 6;   /* Warning Status                  */ 
// sbit EPASS    = CAN0STA ^ 5;   /* Error Passive                   */
// sbit RXOK     = CAN0STA ^ 4;   /* Received Message Successfully   */
// sbit TXOK     = CAN0STA ^ 3;   /* Transmit a Message Successfully */
// sbit LEC2     = CAN0STA ^ 2;   /* Last error code bit 2           */
// sbit LEC1     = CAN0STA ^ 1;   /* Last error code bit 1           */
// sbit LEC0     = CAN0STA ^ 0;   /* Last error code bit 0           */

// sfr  CAN0TST  = 0xDB;          /* CAN 0 TEST                      */


/* Message Object Structure in the Message Memory */
/* UMask  Msk28-0 MXtd MDir EoB    NewDat      MsgLst RxIE  TxIE  IntPnd RmtEn TxRqst */
/* MsgVal ID28-0  Xtd  Dir  DLC3-0 Data0 Data1 Data2  Data3 Data4 Data5  Data6 Data7  */

/***********************************************************************
 * CAN Protocol Register Index for CAN0ADR
 ***********************************************************************/
#define CANCTRL      0x00       //Control Register
#define CANSTAT      0x01       //Status register

#define ERRCNT       0x02       //Error Counter Register
// Bit15: RP, Receive Error Passive
//     1: The Receive Error Counter has reached the error passive level as in the CAN Specification.
//     0: The Receive Error Counter is below the error passivelevel.
// Bit[14..8]: REC6-0, Receive  Error Counter, Actual state of the Receive Error Counter. Values between 0 and 127.
// Bit[7..0]:  TEC7-0, Transmit Error Counter, Actual state of the Transmit Error Counter. Values between 0 and 255.

#define BITREG       0x03       //Bit Timing Register
// Bit[15..12]: TSeg2, The time segment after  the sample point <0x01-0x0F>.
// Bit[11..8]:  TSeg1, The time segment before the sample point <0x01-0x0F>.
// Bit[7..6]:   SJW, (Re)Synchronisation Jump Width, <0x0-0x3>.
// Bit[5..0]:   BRP, Baud Rate Prescaler <0x01-0x3F>.
#define BRPEXT       0x06       //BRP Extension Register
// Bit[3..0]: BRPE, Baud Rate Prescaler Extension <0x00-0x0F>.
// BRPE (MSBs) and BRP (LSBs) is used. 
// Baud Rate Prescaler can be extended to 1023 <BRPEXT[3..0]_BRP[5..0]>. 

#define INTREG       0x04       //Interrupt Low Byte Register

#define CANTSTR      0x05       //Test register
// Bit7: Rx Monitors the actual value of the CAN_RX Pin
//  0/1: The CAN bus is dominant (CAN_RX = ‘0’) / recessive (CAN_RX = ‘1’).
// Bit[6..5]: Tx1-0 Control of CAN_TX pin
//        00: Reset value, CAN_TX is controlled by the CAN Core.
//        01: Sample Point can be monitored at CAN_TX pin.
//        10: CAN_TX pin drives a dominant (‘0’) value.
//        11: CAN_TX pin drives a recessive(‘1’) value.
// Bit4: LBack Loop Back Mode.
// Bit3: Silent Silent Mode.
// Bit2: Basic Basic Mode.
//    1: IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
//    0: Basic Mode disabled.

/***********************************************************************
 * IF1 Interface Registers
 ***********************************************************************/
#define IF1CMDRQST   0x08       //IF1 Command Rest      Register
// Bit15: Busy Busy Flag.
//     0: Read/write action has finished.
//     1: Writing to the IFx Command Request Register.
// Bit[5..0]: Message Number.
// 0x01-0x20: Valid Message Number, the Message Object in the Message
// 0x00 and 0x21-0x3F: Not a valid Message Number, interpreted as 0x20.

#define IF1CMDMSK    0x09       //IF1 Command Mask      Register
// Bit7: WR/RD,
//    1: Transfer data from the selected Message Buffer Registers to the
//       Message Object addressed by the Command Request Register.
//    0: Transfer data from the Message Object addressed by the Command
//       Request Register into the selected Message Buffer Registers.
// The other bits of IFx Command Mask Register have different functions depending on the transfer direction.

// Bit6: Mask (Access Mask Bits) 
//       Direction = Write.
//    1: transfer Identifier Mask + MDir + MXtd to Message Object.
//    0: Mask bits unchanged.
//       Direction = Read.
//    1: transfer Identifier Mask + MDir + MXtd to IFx Message Buffer Register.
//    0: Mask bits unchanged.

// Bit5: Arb (Access Arbitration Bits)
//       Direction = Write.
//    1: transfer Identifier + Dir + Xtd + MsgVal to Message Object.
//    0: Arbitration bits unchanged.
//       Direction = Read.
//    1: transfer Identifier + Dir + Xtd + MsgVal to IFx Message Buffer Register.
//    0: Arbitration bits unchanged.

// Bit4: Control (Access Control Bits)
//       Direction = Write.
//    1: transfer Control Bits to Message Object. 
//    0: Control bits unchanged.
//       Direction = Read.
//    1: transfer Control Bits to IFx Message Buffer Register.
//    0: Control bits unchanged.

// Bit3: ClrIntPnd (Clear Interrupt Pending Bit)
//       Direction = Write, Ignored.
//       Direction = Read.
//    1: Clear IntPnd bit in the Message Object.
//    0: ClrIntPnd bits unchanged.

// Bit2: TxRqst/NewDat (Access New Data Bit)
//       Direction = Write.
//    1: set TxRqst bit.
//    0: TxRqst bit unchanged.
//       Direction = Read.
//    1: clear NewDat bit in the Message Object.
//    0: NewDat bit remains unchanged.

// Bit1: Data A (Access Data Bytes 0-3)
//       Direction = Write.
//    1: transfer Control Bits to Message Object. 
//    0: Control bits unchanged.
//       Direction = Read.
//    1: transfer Control Bits to IFx Message Buffer Register.
//    0: Control bits unchanged.

// Bit0: Data B (Access Data Bytes 4-7)
//       Direction = Write.
//    1: transfer Control Bits to Message Object. 
//    0: Control bits unchanged.
//       Direction = Read.
//    1: transfer Control Bits to IFx Message Buffer Register.
//    0: Control bits unchanged.

/* IFx Message Buffer Registers */
#define IF1MSK1      0x0A       //IF1 Mask1             Register
// Bit[15..0]: Msk15-0.
#define IF1MSK2      0x0B       //IF1 Mask2             Register
// Bit15: MXtd.
// Bit14: MDir.
// Bit13: res.
// Bit[12..0]: Msk28-16.

#define IF1ARB1      0x0C       //IF1 Arbitration 1     Register
// Bit[15..0]:  ID15-0.
#define IF1ARB2      0x0D       //IF1 Arbitration 2     Register
// Bit15: MsgVal.
// Bit14: Xtd.
// Bit13: Dir.
// Bit[12..0]: ID28-16.

#define IF1MSGC      0x0E       //IF1 Message Control   Register
// Bit15: NewDat.
// Bit14: MsgLst.
// Bit13: IntPnd.
// Bit12: UMask.
// Bit11: TxIE.
// Bit10: RxIE.
// Bit9:  RmtEn.
// Bit8:  TxRqst.
// Bit7:  EoB.
// Bit[6..4]: res.
// Bit[3..0]: DLC3-0.         

#define IF1DATA1     0x0F       //IF1 Data A1           Register
#define IF1DATA2     0x10       //IF1 Data A2           Register
#define IF1DATB1     0x11       //IF1 Data B1           Register
#define IF1DATB2     0x12       //IF1 Data B2           Register

/***********************************************************************
 * IF2 Interface Registers
 ***********************************************************************/
#define IF2CMDRQST   0x20       //IF2 Command Rest      Register
#define IF2CMDMSK    0x21       //IF2 Command Mask      Register
#define IF2MSK1      0x22       //IF2 Mask1             Register
#define IF2MSK2      0x23       //IF2 Mask2             Register
#define IF2ARB1      0x24       //IF2 Arbitration 1     Register
#define IF2ARB2      0x25       //IF2 Arbitration 2     Register
#define IF2MSGC      0x26       //IF2 Message Control   Register
#define IF2DATA1     0x27       //IF2 Data A1           Register
#define IF2DATA2     0x28       //IF2 Data A2           Register
#define IF2DATB1     0x29       //IF2 Data B1           Register
#define IF2DATB2     0x2A       //IF2 Data B2           Register

/***********************************************************************
 * Message Handler Registers
 ***********************************************************************/
#define TRANSREQ1    0x40       //Transmission Rest1 Register
#define TRANSREQ2    0x41       //Transmission Rest2 Register

#define NEWDAT1      0x48       //New Data 1            Register
#define NEWDAT2      0x49       //New Data 2            Register

#define INTPEND1     0x50       //Interrupt Pending 1   Register
#define INTPEND2     0x51       //Interrupt Pending 2   Register

#define MSGVAL1      0x58       //Message Valid 1       Register
#define MSGVAL2      0x59       //Message Valid 2       Register

/****************************************************************************
** 函数名称: CAN_Init(void)
** 功能描述: 初始化CAN控制器定时、波特率，使能CAN控制器
** 入口参数: 无
** 出口参数: 无
** 全局变量: 无
** 调用模块: 无
** 说明: 
****************************************************************************/
extern void CAN_Init(void);

/****************************************************************************
** 函数名称: CAN_ClrMsgObject(void)
** 功能描述: 清除所有CAN控制器msg object.
** 入口参数: 无
** 出口参数: 无
** 全局变量: 无
** 调用模块: 无
** 说明: 
****************************************************************************/
extern void CAN_ClrMsgObject(void);


/****************************************************************************
** 函数名称: CAN_RunCtrl(bit RunCtrl)
** 功能描述: 启动/停止CAN控制器
** 入口参数: 无
** 出口参数: 无
** 全局变量: 无
** 调用模块: 无
** 说明: 
****************************************************************************/
extern void CAN_RunCtrl(bit RunCtrl);


/****************************************************************************
** 函数名称: CAN_SendMsg()
** 功能描述: 发送msg.
** 入口参数: 无
** 出口参数: 无
** 全局变量: 无
** 调用模块: 无
** 说明: 
****************************************************************************/
extern void CAN_SendMsg(unsigned char MsgNum, unsigned char ByteNum);

/****************************************************************************
** 函数名称: CAN_RecvMsg()
** 功能描述: 接收msg.
** 入口参数: 无
** 出口参数: 无
** 全局变量: 无
** 调用模块: 无
** 说明: 
****************************************************************************/
extern void CAN_RecvMsg(unsigned char MsgNum);


#endif /* END OF CAN */
/**********END OF FILE******************************************************/