📄 can.c
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CAN_RecvDATA[2] = CAN0DATH;
CAN_RecvDATA[3] = CAN0DATL;
CAN_RecvDATA[4] = CAN0DATH;
CAN_RecvDATA[5] = CAN0DATL;
CAN_RecvDATA[6] = CAN0DATH;
CAN_RecvDATA[7] = CAN0DATL;
}
*/
/****************************************************************************
** 函数名称: CAN_ISR()
** 功能描述: CAN控制器中断服务程序.
** 入口参数: 无
** 出口参数: 无
** 全局变量: 无
** 调用模块: 无
** 说明:
****************************************************************************/
/*
void CAN_ISR(void) interrupt 19
{
unsigned char CanSTATUS, ucTMP;
CanSTATUS = CAN0STA;
// Bit7: BOff: Busoff Status;
// 0/1: Not BusOff / BusOff.
// Bit6: EWarn: Warning Status;
// 0/1: BothEML < 96 / At Least OneEML > 96.
// Bit5: EPass: Error Passive;
// 0/1: CAN Core IS Error Active / error passive state.
// Bit4: RxOk: Received a Message Successfully, Cleared by SoftWare.
// Bit3: TxOk: Transmitted a Message Successfully, Cleared by SoftWare.
// Bit[2..0]: LEC[2..0]: Last Error Code. Type of the last error to occur on the CAN bus
// 0: No Error
// 1: Stuff Error: 位填充错误
// 2: Form Error: 接收帧格式错误
// 3: AckError: 对方接收CAN控制器无应答
// 4: Bit1Error: 发送隐性电平“1”，监测为“0”
// 5: Bit0Error: 发送显性电平“0”，监测为“1”，应答错误等
// 6: CRCError: 接收数据的CRC校验码错误
// 7: Unused: 无CAN事件发生
if( (CanSTATUS&0x10) != 0 ) // RX OK.
{
CAN0STA = (CAN0STA & 0xEF) | 0x07; // Reset RxOk, Set LEC to NoChange
receive_data (0x01); // Up to now, we have only one RX message
}
if( (CanSTATUS&0x08) != 0) // Tx OK.
{
CAN0STA = (CAN0STA & 0xF7) | 0x07; // Reset TxOk, set LEC to NoChange
}
ucTMP = CanSTATUS & 0x07;
if( ( ucTMP != 0) && ( ucTMP != 7) ) // Not Equal 0 AND Equal 7.
{ // CAN Controllor Error Process.
switch( ucTMP )
{
case 1:
break;
case 2:
break;
case 3:
break;
case 4:
break;
case 5:
break;
case 6:
break;
default:
break;
}
CAN0STA = CAN0STA | 0x07; // Set LEC to NoChange
}
}
*/
/*
CAN0CN / CANCTRL // CAN Control Register
// Configuration Change Enable CCE and INIT
// Bit7: CAN Test Mode Enable bit.
// Bit6: CAN Configuration Change Enable bit, "CCE".
// Bit5: CAN Disable Automatic Retransmission bit.
// Bit4: CAN Module Interrupt Flag.
// Bit3: CAN Module Error Interrupt Enable Bit.
// Bit2: CAN Status change Interrupt Enable Bit.
// Bit1: CAN Module Interrupt Enable Bit, "INIT".
// Bit0: CAN Initialization bit.
CAN0STA / CANSTAT // Status Register
// Bit7: BOff: Busoff Status; 0/1: Not BusOff / BusOff.
// Bit6: EWarn: Warning Status;0/1: BothEML < 96 / At Least OneEML > 96.
// Bit5: EPass: Error Passive; 0/1: CAN Core IS Error Active / error passive state.
// Bit4: RxOk: Received a Message Successfully. Cleared by SoftWare.
// Bit3: TxOk: Transmitted a Message Successfully.Cleared by SoftWare.
// Bit[2..0]: LEC[2..0]: Last Error Code. Type of the last error to occur on the CAN bus
// 0: No Error
// 1: Stuff Error: 位填充错误
// 2: Form Error: 接收帧格式错误
// 3: AckError: 对方接收CAN控制器无应答
// 4: Bit1Error: 发送隐性电平“1”，监测为“0”
// 5: Bit0Error: 发送显性电平“0”，监测为“1”，应答错误等
// 6: CRCError: 接收数据的CRC校验码错误
// 7: Unused: 无CAN事件发生
CAN0TST / CANTEST // Test Register
// Bit7: Rx: Monitors the actual value of the CAN_RX Pin; 0/1 <==> CAN_RX.
// BIt[6..5]: Tx1-0: Control of CAN_TX pin
// 00: Reset value, CAN_TX is controlled by the CAN Core.
// 01: Sample Point can be monitored at CAN_TX pin.
// 10: CAN_TX pin drives a dominant (‘0’) value.
// 11: CAN_TX pin drives a recessive (‘1’) value.
// Bit4: 0/1: Loop Back Mode is Disabled / Enabled.
// Bit3: 0/1: Normal / Silent Silent Mode
// Bit2: 0/1: Basic Mode Is Disabled / Enabled.
// In Basic Mode, IF1 Used as Tx Buffer, IF2 Used as Rx Buffer.
ERRCNT // Error Counter
// Bit15: RP: Receive Error Passive; 0/1: Below / Reached the error passivelevel
// Bit[14..]: REC[6..0] Receive Error Counter,Values between 0 and 127.
// Bit[7..0]: TEC[7..0] Transmit Error Counter,Values between 0 and 255.
BITREG // Bit Timing Register.
// Bit[14..12]: TSeg2, the time segment AFTER the sample point, 0x01-0x07.
// Bit[11..8]: TSeg1, the time segment BEFORE the sample point, 0x01-0x0F.
// Bit[7..6]: SJW, (Re)Synchronisation Jump Width, 0x00-0x03.
// Bit[5..0]: BRP, Baud Rate Prescaler, 0x01-0x3F.
BRPEXT // BRP Extension Register.
// Bit[3..0]: BRPE, Baud Rate Prescaler Extension, 0x00-0x0F.
// Baud Rate Prescaler = BRPE(MSBs) | BRP (LSBs).
INTREG // Interrupt Register.
// BIt[15..8]: IntId[15..0],
// 0x0000 No interrupt is pending.
// 0x0001-0x0020 Number of Message Object which caused the interrupt.
// 0x0021-0x7FFF unused.
// 0x8000 Status Interrupt.
// 0x8001-0xFFFF unused
/////////////////////////////////////////////////////////////////////////////
// Message Interface Register Sets //
/////////////////////////////////////////////////////////////////////////////
IF1CMDRQST // IF1 Command Request Registers.
// Bit15: Busy Busy Flag. Set to '1' when writing to the IFx Command Request Register
// Reset to '0' when read/write action has finished.
// Bit[5..0]: Message Number
// 0x01-0x20 Valid Message Number.
// 0x00 Not a valid Message Number, interpreted as 0x20.
// 0x21-0x3F Not a valid Message Number, interpreted as 0x01-0x1F.
IF1CMDMSK // IF1 Command Mask Registers.
// Bit7: WR/RD, 0/1: Write/Read.
// If Direction = Write.
// Bit6: Mask, 0/1: Mask bits unchanged / Transfer Identifier Mask + MDir + MXtd to Message Object.
// Bit5: Arb, 0/1: Arb bits unchanged / Transfer Identifier + Dir + Xtd + MsgVal to Message Object.
// Bit4: Control, 0/1: Control Bits unchanged / Transfer Control Bits to Message Object.
// Bit3: ClrIntPnd, When writing to a Message Object, this bit is ignored.
// Bit2: TxRqst/NewDat, 0/1: TxRqst bit unchanged / Set TxRqst bit.
// Bit1: Data A, 0/1: Data Bytes0-3 unchanged / Transfer Data Bytes0-3 to Message Object.
// Bit0: Data B, 0/1: Data Bytes4-7 unchanged / Transfer Data Bytes4-7 to Message Object.
// If Direction = Read.
// Bit6: Mask, 0/1: Mask bits unchanged / Transfer Identifier Mask + MDir + MXtd to IFx Message Buffer Register.
// Bit5: Arb, 0/1: Arb bits unchanged / Transfer Identifier + Dir + Xtd + MsgVal to IFx Message Buffer Register.
// Bit4: Control, 0/1: Control Bits unchanged / Transfer Control Bits to IFx Message Buffer Register.
// Bit3: ClrIntPnd: 0/1: IntPnd bit remains unchanged / Clear IntPnd bit in the Message Object.
// Bit2: TxRqst/NewDat: 0/1: NewDat bit remains unchanged / Clear NewDat bit in the Message Object.
// Bit1: Data A, 0/1: Data Bytes 0-3 unchanged / Transfer Data Bytes 0-3 to IFx Message Buffer Register.
// Bit0: Data B, 0/1: Data Bytes 4-7 unchanged / Transfer Data Bytes 4-7 to IFx Message Buffer Register.
IF1MSK1 // IF1 Mask 1 Registers
// Bit[15..0]: Msk[15..0].
IF1MSK2 // IF1 Mask 2 Registers
// Bit15: MXtd = 1: The extended identifier bit (IDE) is used for acceptance filtering.
// Bit14: MDir.
// Bit[12..0]: Msk[28..16].
IF1ARB1 // IF1 Arbitration 1 Registers
// Bit[15..0]: ID[15..0].
IF1ARB2 // IF1 Arbitration 2 Registers
// Bit15: MsgVal = 1: Message is Valid.
// Bit14: Xtd = 1: The 29-bit Identifier will be used.
// Bit13: Dir.
// Bit[12..0]: ID[28..16].
IF1MSGC // IF1 Message Control Registers
// Bit15: NewDat:
// Bit14: MsgLst:
// Bit13: IntPnd:
// Bit12: UMask:
// Bit11: TxIE:
// Bit10: RxIE:
// Bit9: RmtEn:
// Bit8: TxRqst:
// Bit7: EoB:
// Bit[3..0]: DLC[3..0].
// Message Object Structure.
// UMask Msk28-0 MXtd MDir EoB NewDat MsgLst RxIE TxIE IntPnd RmtEn TxRqst
// MsgVal ID28-0 Xtd Dir DLC3-0 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7
// MsgVal: Message Valid
// 1: The Message Object is configured and should be considered by the Message Handler.
// 0: The Message Object is ignored by the Message Handler.
// UMask: Use Acceptance Mask
// 1: Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering
// 0: Mask ignored.
// ID[28..0]: Message Identifier
// ID[28..0]: 29-bit Identifier (“Extended Frame”).
// ID[28..18]: 11-bit Identifier (“Standard Frame”).
// Msk[28..0]: Identifier Mask
// 1: The corresponding identifier bit is used for acceptance filtering.
// 0: The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
// Xtd: Extended Identifier Enabiled(1) / Disabled(0).
// MXtd: Mask Extended Identifier Enabiled(1) / Disabled(0).
// Dir: Message Direction, 0/1: Receive / Transmit.
// MDir: Mask Message Direction, 0/1: No effect / Acceptance filtering
// EoB: End of Buffer, 0/1: MsgOBJ Isn't / Is the Last Message of FIFO.
// NewDat: New Data(1).
// MsgLst: Message Lost(1).
// RxIE: Receive Interrupt Enable(1) or Disable(0).
// TxIE: Transmit Interrupt Enable(1) or Disable(0).
// IntPnd: Interrupt Pending. This message object isn't / is the source of an interrupt.
// RmtEn: Remote Enable(1), At the reception of a Remote Frame, TxRqst is set.
// TxRqst: Transmit Request(1), The transmission is not yet done.
// DLC[3..0]: Data Length Code
// 0..8: Data Frame has 0..8 data bytes.
// 9..15: Data Frame has 8 data bytes
TRANSREQ1 // Transmission Request Registers 1. <Read Only>
// Bit[15..8]: TxRqst[16..9].
// Bit[7..0]: TxRqst[8..0].
TRANSREQ2 // Transmission Request Registers 2. <Read Only>
// Bit[31..24]: TxRqst[32..25].
// Bit[23..16]: TxRqst[24..17].
NEWDAT1 // New Data Registers 1. <Read Only>
// Bit[15..8]: NewDat[16..9].
// Bit[7..0]: NewDat[8..0].
NEWDAT2 // New Data Registers 2. <Read Only>
// Bit[31..24]: NewDat[32..25].
// Bit[23..16]: NewDat[24..17].
INTPEND1 // Interrupt Pending Registers 1. <Read Only>
// Bit[15..8]: IntPnd[16..9].
// Bit[7..0]: IntPnd[8..0].
INTPEND2 // Interrupt Pending Registers 2. <Read Only>
// Bit[31..24]: IntPnd[32..25].
// Bit[23..16]: IntPnd[24..17].
MSGVAL1 // Message Valid 1 Register 1. <Read Only>
// Bit[15..8]: MsgVal[16..9].
// Bit[7..0]: MsgVal[8..0].
MSGVAL2 // Message Valid 1 Register 2. <Read Only>
// Bit[31..24]: MsgVal[32..25].
// Bit[23..16]: MsgVal[24..17].
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