io_map.h

DSP56F8367 DEMO CODE

  #define SEMI_CSTC_4_MDAR2_MASK        4U
  #define SEMI_CSTC_4_RWSH0_MASK        256U
  #define SEMI_CSTC_4_RWSH1_MASK        512U
  #define SEMI_CSTC_4_RWSS0_MASK        1024U
  #define SEMI_CSTC_4_RWSS1_MASK        2048U
  #define SEMI_CSTC_4_WWSH0_MASK        4096U
  #define SEMI_CSTC_4_WWSH1_MASK        8192U
  #define SEMI_CSTC_4_WWSS0_MASK        16384U
  #define SEMI_CSTC_4_WWSS1_MASK        32768U
  #define SEMI_CSTC_4_MDAR_MASK         7U
  #define SEMI_CSTC_4_MDAR_BITNUM       0U
  #define SEMI_CSTC_4_RWSH_MASK         768U
  #define SEMI_CSTC_4_RWSH_BITNUM       8U
  #define SEMI_CSTC_4_RWSS_MASK         3072U
  #define SEMI_CSTC_4_RWSS_BITNUM       10U
  #define SEMI_CSTC_4_WWSH_MASK         12288U
  #define SEMI_CSTC_4_WWSH_BITNUM       12U
  #define SEMI_CSTC_4_WWSS_MASK         49152U
  #define SEMI_CSTC_4_WWSS_BITNUM       14U
  #define SEMI_CSTC_4                   *((volatile word *)0x0000F034)


  /*** SEMI_CSTC_5 - SEMI CS Timing Control Register 5; 0x0000F035 ***/
  union {
    word Word;
  } SEMI_CSTC_5_STR;
  
  #define SEMI_CSTC_5_MDAR0_MASK        1U
  #define SEMI_CSTC_5_MDAR1_MASK        2U
  #define SEMI_CSTC_5_MDAR2_MASK        4U
  #define SEMI_CSTC_5_RWSH0_MASK        256U
  #define SEMI_CSTC_5_RWSH1_MASK        512U
  #define SEMI_CSTC_5_RWSS0_MASK        1024U
  #define SEMI_CSTC_5_RWSS1_MASK        2048U
  #define SEMI_CSTC_5_WWSH0_MASK        4096U
  #define SEMI_CSTC_5_WWSH1_MASK        8192U
  #define SEMI_CSTC_5_WWSS0_MASK        16384U
  #define SEMI_CSTC_5_WWSS1_MASK        32768U
  #define SEMI_CSTC_5_MDAR_MASK         7U
  #define SEMI_CSTC_5_MDAR_BITNUM       0U
  #define SEMI_CSTC_5_RWSH_MASK         768U
  #define SEMI_CSTC_5_RWSH_BITNUM       8U
  #define SEMI_CSTC_5_RWSS_MASK         3072U
  #define SEMI_CSTC_5_RWSS_BITNUM       10U
  #define SEMI_CSTC_5_WWSH_MASK         12288U
  #define SEMI_CSTC_5_WWSH_BITNUM       12U
  #define SEMI_CSTC_5_WWSS_MASK         49152U
  #define SEMI_CSTC_5_WWSS_BITNUM       14U
  #define SEMI_CSTC_5                   *((volatile word *)0x0000F035)


  /*** SEMI_CSTC_6 - SEMI CS Timing Control Register 6; 0x0000F036 ***/
  union {
    word Word;
  } SEMI_CSTC_6_STR;
  
  #define SEMI_CSTC_6_MDAR0_MASK        1U
  #define SEMI_CSTC_6_MDAR1_MASK        2U
  #define SEMI_CSTC_6_MDAR2_MASK        4U
  #define SEMI_CSTC_6_RWSH0_MASK        256U
  #define SEMI_CSTC_6_RWSH1_MASK        512U
  #define SEMI_CSTC_6_RWSS0_MASK        1024U
  #define SEMI_CSTC_6_RWSS1_MASK        2048U
  #define SEMI_CSTC_6_WWSH0_MASK        4096U
  #define SEMI_CSTC_6_WWSH1_MASK        8192U
  #define SEMI_CSTC_6_WWSS0_MASK        16384U
  #define SEMI_CSTC_6_WWSS1_MASK        32768U
  #define SEMI_CSTC_6_MDAR_MASK         7U
  #define SEMI_CSTC_6_MDAR_BITNUM       0U
  #define SEMI_CSTC_6_RWSH_MASK         768U
  #define SEMI_CSTC_6_RWSH_BITNUM       8U
  #define SEMI_CSTC_6_RWSS_MASK         3072U
  #define SEMI_CSTC_6_RWSS_BITNUM       10U
  #define SEMI_CSTC_6_WWSH_MASK         12288U
  #define SEMI_CSTC_6_WWSH_BITNUM       12U
  #define SEMI_CSTC_6_WWSS_MASK         49152U
  #define SEMI_CSTC_6_WWSS_BITNUM       14U
  #define SEMI_CSTC_6                   *((volatile word *)0x0000F036)


  /*** SEMI_CSTC_7 - SEMI CS Timing Control Register 7; 0x0000F037 ***/
  union {
    word Word;
  } SEMI_CSTC_7_STR;
  
  #define SEMI_CSTC_7_MDAR0_MASK        1U
  #define SEMI_CSTC_7_MDAR1_MASK        2U
  #define SEMI_CSTC_7_MDAR2_MASK        4U
  #define SEMI_CSTC_7_RWSH0_MASK        256U
  #define SEMI_CSTC_7_RWSH1_MASK        512U
  #define SEMI_CSTC_7_RWSS0_MASK        1024U
  #define SEMI_CSTC_7_RWSS1_MASK        2048U
  #define SEMI_CSTC_7_WWSH0_MASK        4096U
  #define SEMI_CSTC_7_WWSH1_MASK        8192U
  #define SEMI_CSTC_7_WWSS0_MASK        16384U
  #define SEMI_CSTC_7_WWSS1_MASK        32768U
  #define SEMI_CSTC_7_MDAR_MASK         7U
  #define SEMI_CSTC_7_MDAR_BITNUM       0U
  #define SEMI_CSTC_7_RWSH_MASK         768U
  #define SEMI_CSTC_7_RWSH_BITNUM       8U
  #define SEMI_CSTC_7_RWSS_MASK         3072U
  #define SEMI_CSTC_7_RWSS_BITNUM       10U
  #define SEMI_CSTC_7_WWSH_MASK         12288U
  #define SEMI_CSTC_7_WWSH_BITNUM       12U
  #define SEMI_CSTC_7_WWSS_MASK         49152U
  #define SEMI_CSTC_7_WWSS_BITNUM       14U
  #define SEMI_CSTC_7                   *((volatile word *)0x0000F037)


  /*** SEMI_BCR - SEMI Bus Control Register; 0x0000F038 ***/
  union {
    word Word;
  } SEMI_BCR_STR;
  
  #define SEMI_BCR_BRWS0_MASK           1U
  #define SEMI_BCR_BRWS1_MASK           2U
  #define SEMI_BCR_BRWS2_MASK           4U
  #define SEMI_BCR_BRWS3_MASK           8U
  #define SEMI_BCR_BRWS4_MASK           16U
  #define SEMI_BCR_BWWS0_MASK           32U
  #define SEMI_BCR_BWWS1_MASK           64U
  #define SEMI_BCR_BWWS2_MASK           128U
  #define SEMI_BCR_BWWS3_MASK           256U
  #define SEMI_BCR_BWWS4_MASK           512U
  #define SEMI_BCR_BMDAR0_MASK          4096U
  #define SEMI_BCR_BMDAR1_MASK          8192U
  #define SEMI_BCR_BMDAR2_MASK          16384U
  #define SEMI_BCR_DRV_MASK             32768U
  #define SEMI_BCR_BRWS_MASK            31U
  #define SEMI_BCR_BRWS_BITNUM          0U
  #define SEMI_BCR_BWWS_MASK            992U
  #define SEMI_BCR_BWWS_BITNUM          5U
  #define SEMI_BCR_BMDAR_MASK           28672U
  #define SEMI_BCR_BMDAR_BITNUM         12U
  #define SEMI_BCR                      *((volatile word *)0x0000F038)


  word Reserved0[7];                   /* Reserved (unused) registers */

} SEMI_PRPH;

/******************************************
*** Peripheral TMRA0
*******************************************/
typedef volatile struct {
  /*** TMRA0_CMP1 - Timer A Channel 0 Compare Register #1; 0x0000F040 ***/
  union {
    word Word;
  } TMRA0_CMP1_STR;
  
  #define TMRA0_CMP1_COMPARISON_10_MASK 1U
  #define TMRA0_CMP1_COMPARISON_11_MASK 2U
  #define TMRA0_CMP1_COMPARISON_12_MASK 4U
  #define TMRA0_CMP1_COMPARISON_13_MASK 8U
  #define TMRA0_CMP1_COMPARISON_14_MASK 16U
  #define TMRA0_CMP1_COMPARISON_15_MASK 32U
  #define TMRA0_CMP1_COMPARISON_16_MASK 64U
  #define TMRA0_CMP1_COMPARISON_17_MASK 128U
  #define TMRA0_CMP1_COMPARISON_18_MASK 256U
  #define TMRA0_CMP1_COMPARISON_19_MASK 512U
  #define TMRA0_CMP1_COMPARISON_110_MASK 1024U
  #define TMRA0_CMP1_COMPARISON_111_MASK 2048U
  #define TMRA0_CMP1_COMPARISON_112_MASK 4096U
  #define TMRA0_CMP1_COMPARISON_113_MASK 8192U
  #define TMRA0_CMP1_COMPARISON_114_MASK 16384U
  #define TMRA0_CMP1_COMPARISON_115_MASK 32768U
  #define TMRA0_CMP1_COMPARISON__10_MASK 1023U
  #define TMRA0_CMP1_COMPARISON__10_BITNUM 0U
  #define TMRA0_CMP1_COMPARISON_1_10_MASK 64512U
  #define TMRA0_CMP1_COMPARISON_1_10_BITNUM 10U
  #define TMRA0_CMP1                    *((volatile word *)0x0000F040)


  /*** TMRA0_CMP2 - Timer A Channel 0 Compare Register #2; 0x0000F041 ***/
  union {
    word Word;
  } TMRA0_CMP2_STR;
  
  #define TMRA0_CMP2_COMPARISON_20_MASK 1U
  #define TMRA0_CMP2_COMPARISON_21_MASK 2U
  #define TMRA0_CMP2_COMPARISON_22_MASK 4U
  #define TMRA0_CMP2_COMPARISON_23_MASK 8U
  #define TMRA0_CMP2_COMPARISON_24_MASK 16U
  #define TMRA0_CMP2_COMPARISON_25_MASK 32U
  #define TMRA0_CMP2_COMPARISON_26_MASK 64U
  #define TMRA0_CMP2_COMPARISON_27_MASK 128U
  #define TMRA0_CMP2_COMPARISON_28_MASK 256U
  #define TMRA0_CMP2_COMPARISON_29_MASK 512U
  #define TMRA0_CMP2_COMPARISON_210_MASK 1024U
  #define TMRA0_CMP2_COMPARISON_211_MASK 2048U
  #define TMRA0_CMP2_COMPARISON_212_MASK 4096U
  #define TMRA0_CMP2_COMPARISON_213_MASK 8192U
  #define TMRA0_CMP2_COMPARISON_214_MASK 16384U
  #define TMRA0_CMP2_COMPARISON_215_MASK 32768U
  #define TMRA0_CMP2_COMPARISON__20_MASK 1023U
  #define TMRA0_CMP2_COMPARISON__20_BITNUM 0U
  #define TMRA0_CMP2_COMPARISON_2_10_MASK 64512U
  #define TMRA0_CMP2_COMPARISON_2_10_BITNUM 10U
  #define TMRA0_CMP2                    *((volatile word *)0x0000F041)


  /*** TMRA0_CAP - Timer A Channel 0 Capture Register; 0x0000F042 ***/
  union {
    word Word;
  } TMRA0_CAP_STR;
  
  #define TMRA0_CAP                     *((volatile word *)0x0000F042)


  /*** TMRA0_LOAD - Timer A Channel 0 Load Register; 0x0000F043 ***/
  union {
    word Word;
  } TMRA0_LOAD_STR;
  
  #define TMRA0_LOAD_LOAD0_MASK         1U
  #define TMRA0_LOAD_LOAD1_MASK         2U
  #define TMRA0_LOAD_LOAD2_MASK         4U
  #define TMRA0_LOAD_LOAD3_MASK         8U
  #define TMRA0_LOAD_LOAD4_MASK         16U
  #define TMRA0_LOAD_LOAD5_MASK         32U
  #define TMRA0_LOAD_LOAD6_MASK         64U
  #define TMRA0_LOAD_LOAD7_MASK         128U
  #define TMRA0_LOAD_LOAD8_MASK         256U
  #define TMRA0_LOAD_LOAD9_MASK         512U
  #define TMRA0_LOAD_LOAD10_MASK        1024U
  #define TMRA0_LOAD_LOAD11_MASK        2048U
  #define TMRA0_LOAD_LOAD12_MASK        4096U
  #define TMRA0_LOAD_LOAD13_MASK        8192U
  #define TMRA0_LOAD_LOAD14_MASK        16384U
  #define TMRA0_LOAD_LOAD15_MASK        32768U
  #define TMRA0_LOAD                    *((volatile word *)0x0000F043)


  /*** TMRA0_HOLD - Timer A Channel 0 Hold Register; 0x0000F044 ***/
  union {
    word Word;
  } TMRA0_HOLD_STR;
  
  #define TMRA0_HOLD_HOLD0_MASK         1U
  #define TMRA0_HOLD_HOLD1_MASK         2U
  #define TMRA0_HOLD_HOLD2_MASK         4U
  #define TMRA0_HOLD_HOLD3_MASK         8U
  #define TMRA0_HOLD_HOLD4_MASK         16U
  #define TMRA0_HOLD_HOLD5_MASK         32U
  #define TMRA0_HOLD_HOLD6_MASK         64U
  #define TMRA0_HOLD_HOLD7_MASK         128U
  #define TMRA0_HOLD_HOLD8_MASK         256U
  #define TMRA0_HOLD_HOLD9_MASK         512U
  #define TMRA0_HOLD_HOLD10_MASK        1024U
  #define TMRA0_HOLD_HOLD11_MASK        2048U
  #define TMRA0_HOLD_HOLD12_MASK        4096U
  #define TMRA0_HOLD_HOLD13_MASK        8192U
  #define TMRA0_HOLD_HOLD14_MASK        16384U
  #define TMRA0_HOLD_HOLD15_MASK        32768U
  #define TMRA0_HOLD                    *((volatile word *)0x0000F044)


  /*** TMRA0_CNTR - Timer A Channel 0 Counter Register; 0x0000F045 ***/
  union {
    word Word;
  } TMRA0_CNTR_STR;
  
  #define TMRA0_CNTR                    *((volatile word *)0x0000F045)


  /*** TMRA0_CTRL - Timer A Channel 0 Control Register; 0x0000F046 ***/
  union {
    word Word;
  } TMRA0_CTRL_STR;
  
  #define TMRA0_CTRL_OM0_MASK           1U
  #define TMRA0_CTRL_OM1_MASK           2U
  #define TMRA0_CTRL_OM2_MASK           4U
  #define TMRA0_CTRL_Co_INIT_MASK       8U
  #define TMRA0_CTRL_DIR_MASK           16U
  #define TMRA0_CTRL_LENGTH_MASK        32U
  #define TMRA0_CTRL_ONCE_MASK          64U
  #define TMRA0_CTRL_SCS0_MASK          128U
  #define TMRA0_CTRL_SCS1_MASK          256U
  #define TMRA0_CTRL_PCS0_MASK          512U
  #define TMRA0_CTRL_PCS1_MASK          1024U
  #define TMRA0_CTRL_PCS2_MASK          2048U
  #define TMRA0_CTRL_PCS3_MASK          4096U
  #define TMRA0_CTRL_CM0_MASK           8192U
  #define TMRA0_CTRL_CM1_MASK           16384U
  #define TMRA0_CTRL_CM2_MASK           32768U
  #define TMRA0_CTRL_OM_MASK            7U
  #define TMRA0_CTRL_OM_BITNUM          0U
  #define TMRA0_CTRL_SCS_MASK           384U
  #define TMRA0_CTRL_SCS_BITNUM         7U
  #define TMRA0_CTRL_PCS_MASK           7680U
  #define TMRA0_CTRL_PCS_BITNUM         9U
  #define TMRA0_CTRL_CM_MASK            57344U
  #define TMRA0_CTRL_CM_BITNUM          13U
  #define TMRA0_CTRL                    *((volatile word *)0x0000F046)


  /*** TMRA0_SCR - Timer A Channel 0 Status and Control Register; 0x0000F047 ***/
  union {
    word Word;
  } TMRA0_SCR_STR;
  
  #define TMRA0_SCR_OEN_MASK            1U
  #define TMRA0_SCR_OPS_MASK            2U
  #define TMRA0_SCR_FORCE_MASK          4U
  #define TMRA0_SCR_VAL_MASK            8U
  #define TMRA0_SCR_EEOF_MASK           16U
  #define TMRA0_SCR_MSTR_MASK           32U
  #define TMRA0_SCR_Capture_Mode0_MASK  64U
  #define TMRA0_SCR_Capture_Mode1_MASK  128U
  #define TMRA0_SCR_INPUT_MASK          256U
  #define TMRA0_SCR_IPS_MASK            512U
  #define TMRA0_SCR_IEFIE_MASK          1024U
  #define TMRA0_SCR_IEF_MASK            2048U
  #define TMRA0_SCR_TOFIE_MASK          4096U
  #define TMRA0_SCR_TOF_MASK            8192U
  #define TMRA0_SCR_TCFIE_MASK          16384U
  #define TMRA0_SCR_TCF_MASK            32768U
  #define TMRA0_SCR_Capture_Mode_MASK   192U
  #define TMRA0_SCR_Capture_Mode_BITNUM 6U
  #define TMRA0_SCR                     *((volatile word *)0x0000F047)


  /*** TMRA0_CMPLD1 - Timer A Channel 0 Comparator Load Register 1; 0x0000F048 ***/
  union {
    word Word;
  } TMRA0_CMPLD1_STR;
  
  #define TMRA0_CMPLD1_COMPARATOR_LOAD_10_MASK 1U