📄 dsp28_device.h
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Uint16 TENABLE:1; // 6 Timer enable
Uint16 T4SWT3:1; // 7 Start GP timer 2 with GP timer 1's enable
Uint16 TPS:3; // 10:8 Input clock prescaler
Uint16 TMODE:2; // 12:11 Count mode selection
Uint16 rsvd:1; // 13 reserved
Uint16 FREE:1; // 14 Free emulation control
Uint16 SOFT:1; // 15 Soft emulation control
};
/* Allow access to the bit fields or entire register */
union TCONB_REG {
Uint16 all;
struct TCONB_BITS bit;
};
struct EXTCONA_BITS {
Uint16 INDCOE:1; // 0 Independant compare output
Uint16 QEPIQEL:1; // 1 QEP/CAP3 Index Qual Mode
Uint16 QEPIE:1; // 2 QEP index enable
Uint16 EVSOCE:1; // 3 Ev start of conversion output enable
Uint16 rsvd:12; // 15:4 reserved
};
/* Allow access to the bit fields or entire register */
union EXTCONA_REG {
Uint16 all;
struct EXTCONA_BITS bit;
};
struct EXTCONB_BITS {
Uint16 INDCOE:1; // 0 Independant compare output
Uint16 QEPIQEL:1; // 1 QEP/CAP3 Index Qual Mode
Uint16 QEPIE:1; // 2 QEP index enable
Uint16 EVSOCE:1; // 3 Ev start of conversion output enable
Uint16 rsvd:12; // 15:4 reserved
};
/* Allow access to the bit fields or entire register */
union EXTCONB_REG {
Uint16 all;
struct EXTCONA_BITS bit;
};
/* Compare Control Register */
struct COMCONA_BITS {
Uint16 rsvd:8; // 7:0 reserved
Uint16 PDPINTASTATUS:1;// 8 Current status of the PDPINTA pin
Uint16 FCOMPOE:1; // 9 Compare output enable
Uint16 ACTRLD:2; // 11:10 Action control register reload
Uint16 SVENABLE:1; // 12 Space vector PWM Mode enable
Uint16 CLD:2; // 14:13 Compare register reload condition
Uint16 CENABLE:1; // 15 Compare enable
};
/* Allow access to the bit fields or entire register */
union COMCONA_REG {
Uint16 all;
struct COMCONA_BITS bit;
};
struct COMCONB_BITS {
Uint16 rsvd:8; // 7:0 reserved
Uint16 PDPINTBSTATUS:1;// 8 Current status of the PDPINTB pin
Uint16 FCOMPOE:1; // 9 Compare output enable
Uint16 ACTRLD:2; // 11:10 Action control register reload
Uint16 SVENABLE:1; // 12 Space vector PWM Mode enable
Uint16 CLD:2; // 14:13 Compare register reload condition
Uint16 CENABLE:1; // 15 Compare enable
};
/* Allow access to the bit fields or entire register */
union COMCONB_REG {
Uint16 all;
struct COMCONB_BITS bit;
};
/* Compare Action Control Register bit definitions */
struct ACTRA_BITS {
Uint16 CMP1ACT:2; // 1:0 Action on compare output pin 1 CMP1
Uint16 CMP2ACT:2; // 3:2 Action on compare output pin 2 CMP2
Uint16 CMP3ACT:2; // 5:4 Action on compare output pin 3 CMP3
Uint16 CMP4ACT:2; // 7:6 Action on compare output pin 4 CMP4
Uint16 CMP5ACT:2; // 9:8 Action on compare output pin 5 CMP5
Uint16 CMP6ACT:2; // 11:10 Action on compare output pin 6 CMP6
Uint16 D:3; // 14:12 Basic vector bits
Uint16 SVRDIR:1; // 15 Space vecor PWM rotation dir
};
/* Allow access to the bit fields or entire register */
union ACTRA_REG {
Uint16 all;
struct ACTRA_BITS bit;
};
struct ACTRB_BITS {
Uint16 CMP7ACT:2; // 1:0 Action on compare output pin 7 CMP7
Uint16 CMP8ACT:2; // 3:2 Action on compare output pin 8 CMP8
Uint16 CMP9ACT:2; // 5:4 Action on compare output pin 9 CMP9
Uint16 CMP10ACT:2; // 7:6 Action on compare output pin 10 CMP10
Uint16 CMP11ACT:2; // 9:8 Action on compare output pin 11 CMP11
Uint16 CMP12ACT:2; // 11:10 Action on compare output pin 12 CMP12
Uint16 D:3; // 14:12 Basic vector bits
Uint16 SVRDIR:1; // 15 Space vecor PWM rotation dir
};
/* Allow access to the bit fields or entire register */
union ACTRB_REG {
Uint16 all;
struct ACTRB_BITS bit;
};
/* Dead-Band Timer Control register bit definitions */
struct DBTCON_BITS {
Uint16 rsvd1:2; // 1:0 reserved
Uint16 DBTPS:3; // 4:2 Dead-Band timer prescaler
Uint16 EDBT1:1; // 5 Dead-Band timer 1 enable
Uint16 EDBT2:1; // 6 Dead-Band timer 2 enable
Uint16 EDBT3:1; // 7 Dead-Band timer 3 enable
Uint16 DBT:4; // 11:8 Dead-Band timer period
Uint16 rsvd2:4; // 15:12 reserved
};
/* Allow access to the bit fields or entire register */
union DBTCON_REG {
Uint16 all;
struct DBTCON_BITS bit;
};
/* Capture Control register bit definitions */
struct CAPCONA_BITS {
Uint16 rsvd1:2; // 1:0 reserved
Uint16 CAP3EDGE:2; // 3:2 Edge Detection for Unit 3
Uint16 CAP2EDGE:2; // 5:4 Edge Detection for Unit 2
Uint16 CAP1EDGE:2; // 7:6 Edge Detection for Unit 1
Uint16 CAP3TOADC:1; // 8 Unit 3 starts the ADC
Uint16 CAP12TSEL:1; // 9 GP Timer selection for Units 1 and 2
Uint16 CAP3TSEL:1; // 10 GP Timer selection for Unit 3
Uint16 rsvd2:1; // 11 reserved
Uint16 CAP3EN:1; // 12 Capture Unit 3 control
Uint16 CAPQEPN:2; // 14:13 Capture Unit 1 and 2 control
Uint16 CAPRES:1; // 15 Capture reset (always reads 0)
};
/* Allow access to the bit fields or entire register */
union CAPCONA_REG {
Uint16 all;
struct CAPCONA_BITS bit;
};
/* Control register bit definitions */
struct CAPCONB_BITS {
Uint16 rsvd1:2; // 1:0 reserved
Uint16 CAP6EDGE:2; // 3:2 Edge Detection for Unit 6
Uint16 CAP5EDGE:2; // 5:4 Edge Detection for Unit 5
Uint16 CAP4EDGE:2; // 7:6 Edge Detection for Unit 4
Uint16 CAP6TOADC:1; // 8 Unit 6 starts the ADC
Uint16 CAP45TSEL:1; // 9 GP Timer selection for Units 4 and 5
Uint16 CAP6TSEL:1; // 10 GP Timer selection for Unit 6
Uint16 rsvd2:1; // 11 reserved
Uint16 CAP6EN:1; // 12 Capture Unit 6 control
Uint16 CAPQEPN:2; // 14:13 Capture Unit 4 and 5 control
Uint16 CAPRES:1; // 15 Capture reset (always reads 0)
};
/* Allow access to the bit fields or entire register */
union CAPCONB_REG {
Uint16 all;
struct CAPCONB_BITS bit;
};
/* Capture FIFO Status Register bit definitions */
struct CAPFIFOA_BITS {
Uint16 rsvd1:8; // 7:0 reserved
Uint16 CAP1FIFO:2; // 9:8 CAP1 FIFO status
Uint16 CAP2FIFO:2; // 11:10 CAP2 FIFO status
Uint16 CAP3FIFO:2; // 13:12 CAP2 FIFO status
Uint16 rsvd2:2; // 15:14 reserved
};
/* Allow access to the bit fields or entire register */
union CAPFIFOA_REG {
Uint16 all;
struct CAPFIFOA_BITS bit;
};
/* Capture FIFO Status Register bit definitions */
struct CAPFIFOB_BITS {
Uint16 rsvd1:8; // 7:0 reserved
Uint16 CAP4FIFO:2; // 9:8 CAP4 FIFO status
Uint16 CAP5FIFO:2; // 11:10 CAP5 FIFO status
Uint16 CAP6FIFO:2; // 13:12 CAP6 FIFO status
Uint16 rsvd2:2; // 15:14 reserved
};
/* Allow access to the bit fields or entire register */
union CAPFIFOB_REG {
Uint16 all;
struct CAPFIFOB_BITS bit;
};
/* Interrupt Mask Register bit definitions */
struct EVAIMRA_BITS {
Uint16 PDPINTA:1; // 0 Enable PDPINTA
Uint16 CMP1INT:1; // 1 Enable
Uint16 CMP2INT:1; // 2 Enable
Uint16 CMP3INT:1; // 3 Enable
Uint16 rsvd1:3; // 6:4 reserved
Uint16 T1PINT:1; // 7 Enable
Uint16 T1CINT:1; // 8 Enable
Uint16 T1UFINT:1; // 9 Enable
Uint16 T1OFINT:1; // 10 Enable
Uint16 rsvd2:5; // 15:11 reserved
};
/* Allow access to the bit fields or entire register */
union EVAIMRA_REG {
Uint16 all;
struct EVAIMRA_BITS bit;
};
/* Interrupt Mask Register bit definitions */
struct EVBIMRA_BITS {
Uint16 PDPINTB:1; // 0 Enable PDPINTB
Uint16 CMP4INT:1; // 1 Enable
Uint16 CMP5INT:1; // 2 Enable
Uint16 CMP6INT:1; // 3 Enable
Uint16 rsvd1:3; // 6:4 reserved
Uint16 T3PINT:1; // 7 Enable
Uint16 T3CINT:1; // 8 Enable
Uint16 T3UFINT:1; // 9 Enable
Uint16 T3OFINT:1; // 10 Enable
Uint16 rsvd2:5; // 15:11 reserved
};
/* Allow access to the bit fields or entire register */
union EVBIMRA_REG {
Uint16 all;
struct EVBIMRA_BITS bit;
};
struct EVAIMRB_BITS {
Uint16 T2PINT:1; // 0 Enable
Uint16 T2CINT:1; // 1 Enable
Uint16 T2UFINT:1; // 2 Enable
Uint16 T2OFINT:1; // 3 Enable
Uint16 rsvd1:12; // 15:4 reserved
};
/* Allow access to the bit fields or entire register */
union EVAIMRB_REG {
Uint16 all;
struct EVAIMRB_BITS bit;
};
struct EVBIMRB_BITS {
Uint16 T4PINT:1; // 0 Enable
Uint16 T4CINT:1; // 1 Enable
Uint16 T4UFINT:1; // 2 Enable
Uint16 T4OFINT:1; // 3 Enable
Uint16 rsvd1:12; // 15:4 reserved
};
/* Allow access to the bit fields or entire register */
union EVBIMRB_REG {
Uint16 all;
struct EVBIMRB_BITS bit;
};
struct EVAIMRC_BITS {
Uint16 CAP1INT:1; // 0 Enable
Uint16 CAP2INT:1; // 1 Enable
Uint16 CAP3INT:1; // 2 Enable
Uint16 rsvd1:13; // 15:3 reserved
};
/* Allow access to the bit fields or entire register */
union EVAIMRC_REG {
Uint16 all;
struct EVAIMRC_BITS bit;
};
struct EVBIMRC_BITS {
Uint16 CAP4INT:1; // 0 Enable
Uint16 CAP5INT:1; // 1 Enable
Uint16 CAP6INT:1; // 2 Enable
Uint16 rsvd1:13; // 15:3 reserved
};
/* Allow access to the bit fields or entire register */
union EVBIMRC_REG {
Uint16 all;
struct EVBIMRC_BITS bit;
};
/* Interrupt Flag Register bit definitions */
struct EVAIFRA_BITS {
Uint16 PDPINTA:1; // 0 Flag PDPINTA
Uint16 CMP1INT:1; // 1 Flag
Uint16 CMP2INT:1; // 2 Flag
Uint16 CMP3INT:1; // 3 Flag
Uint16 rsvd1:3; // 6:4 reserved
Uint16 T1PINT:1; // 7 Flag
Uint16 T1CINT:1; // 8 Flag
Uint16 T1UFINT:1; // 9 Flag
Uint16 T1OFINT:1; // 10 Flag
Uint16 rsvd2:5; // 15:11 reserved
};
/* Allow access to the bit fields or entire register */
union EVAIFRA_REG {
Uint16 all;
struct EVAIMRA_BITS bit;
};
/* Interrupt Mask Register bit definitions */
struct EVBIFRA_BITS {
Uint16 PDPINTB:1; // 0 Flag PDPINTB
Uint16 CMP4INT:1; // 1 Flag
Uint16 CMP5INT:1; // 2 Flag
Uint16 CMP6INT:1; // 3 Flag
Uint16 rsvd1:3; // 6:4 reserved
Uint16 T3PINT:1; // 7 Flag
Uint16 T3CINT:1; // 8 Flag
Uint16 T3UFINT:1; // 9 Flag
Uint16 T3OFINT:1; // 10 Flag
Uint16 rsvd2:5; // 15:11 reserved
};
/* Allow access to the bit fields or entire register */
union EVBIFRA_REG {
Uint16 all;
struct EVBIFRA_BITS bit;
};
struct EVAIFRB_BITS {
Uint16 T2PINT:1; // 0 Flag
Uint16 T2CINT:1; // 1 Flag
Uint16 T2UFINT:1; // 2 Flag
Uint16 T2OFINT:1; // 3 Flag
Uint16 rsvd1:12; // 15:4 reserved
};
/* Allow access to the bit fields or entire register */
union EVAIFRB_REG {
Uint16 all;
struct EVAIFRB_BITS bit;
};
struct EVBIFRB_BITS {
Uint16 T4PINT:1; // 0 Flag
Uint16 T4CINT:1; // 1 Flag
Uint16 T4UFINT:1; // 2 Flag
Uint16 T4OFINT:1; // 3 Flag
Uint16 rsvd1:12; // 15:4 reserved
};
/* Allow access to the bit fields or entire register */
union EVBIFRB_REG {
Uint16 all;
struct EVBIFRB_BITS bit;
};
struct EVAIFRC_BITS {
Uint16 CAP1INT:1; // 0 Flag
Uint16 CAP2INT:1; // 1 Flag
Uint16 CAP3INT:1; // 2 Flag
Uint16 rsvd1:13; // 15:3 reserved
};
/* Allow access to the bit fields or entire register */
union EVAIFRC_REG {
Uint16 all;
struct EVAIFRC_BITS bit;
};
struct EVBIFRC_BITS {
Uint16 CAP4INT:1; // 0 Flag
Uint16 CAP5INT:1; // 1 Flag
Uint16 CAP6INT:1; // 2 Flag
Uint16 rsvd1:13; // 15:3 reserved
};
/* Allow access to the bit fields or entire register */
union EVBIFRC_REG {
Uint16 all;
struct EVBIFRC_BITS bit;
};
/* EVA Register File */
struct EVA_REGS {
union GPTCONA_REG GPTCONA; //0x7400
Uint16 T1CNT; //0x7401
Uint16 T1CMPR; //0x7402
Uint16 T1PR; //0x7403
union TCONA_REG T1CON; //0x7404
Uint16 T2CNT; //0x7405
Uint16 T2CMPR; //0x7406
Uint16 T2PR; //0x7407
union TCONA_REG T2CON; //0x7408
union EXTCONA_REG EXTCON; //0x7409
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