📄 dsp28_device.h
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PINT CAPINT6; // EV-B
PINT rsvd5_8;
// Group 6 PIE Peripheral Vectors:
PINT SPIRXINTA; // SPI-A
PINT SPITXINTA; // SPI-A
PINT rsvd6_3;
PINT rsvd6_4;
PINT MRINTA; // McBSP-A
PINT MXINTA; // McBSP-A
PINT rsvd6_7;
PINT rsvd6_8;
// Group 7 PIE Peripheral Vectors:
PINT rsvd7_1;
PINT rsvd7_2;
PINT rsvd7_3;
PINT rsvd7_4;
PINT rsvd7_5;
PINT rsvd7_6;
PINT rsvd7_7;
PINT rsvd7_8;
// Group 8 PIE Peripheral Vectors:
PINT rsvd8_1;
PINT rsvd8_2;
PINT rsvd8_3;
PINT rsvd8_4;
PINT rsvd8_5;
PINT rsvd8_6;
PINT rsvd8_7;
PINT rsvd8_8;
// Group 9 PIE Peripheral Vectors:
PINT RXAINT; // SCI-A
PINT TXAINT; // SCI-A
PINT RXBINT; // SCI-B
PINT TXBINT; // SCI-B
PINT ECAN0INTA; // eCAN
PINT ECAN1INTA; // eCAN
PINT rsvd9_7;
PINT rsvd9_8;
// Group 10 PIE Peripheral Vectors:
PINT rsvd10_1;
PINT rsvd10_2;
PINT rsvd10_3;
PINT rsvd10_4;
PINT rsvd10_5;
PINT rsvd10_6;
PINT rsvd10_7;
PINT rsvd10_8;
// Group 11 PIE Peripheral Vectors:
PINT rsvd11_1;
PINT rsvd11_2;
PINT rsvd11_3;
PINT rsvd11_4;
PINT rsvd11_5;
PINT rsvd11_6;
PINT rsvd11_7;
PINT rsvd11_8;
// Group 12 PIE Peripheral Vectors:
PINT rsvd12_1;
PINT rsvd12_2;
PINT rsvd12_3;
PINT rsvd12_4;
PINT rsvd12_5;
PINT rsvd12_6;
PINT rsvd12_7;
PINT rsvd12_8;
};
//---------------------------------------------------------------------------
// PIE Interrupt Vector Table External References & Function Declarations:
//
extern struct PIE_VECT_TABLE PieVectTable;
#endif // end of DSP28_PIE_VECT_H definition
#ifndef DSP28_SYS_CTRL_H
#define DSP28_SYS_CTRL_H
//---------------------------------------------------------------------------
// System Control Individual Register Bit Definitions:
//
// High speed peripheral clock register bit definitions:
struct HISPCP_BITS { // bits description
Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
Uint16 rsvd1:13; // 15:3 reserved
};
union HISPCP_REG {
Uint16 all;
struct HISPCP_BITS bit;
};
// Low speed peripheral clock register bit definitions:
struct LOSPCP_BITS { // bits description
Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
Uint16 rsvd1:13; // 15:3 reserved
};
union LOSPCP_REG {
Uint16 all;
struct LOSPCP_BITS bit;
};
// Peripheral clock control register bit definitions:
struct PCLKCR_BITS { // bits description
Uint16 EVAENCLK:1; // 0 Enable high speed clk to EV-A
Uint16 EVBENCLK:1; // 1 Enable high speed clk to EV-B
Uint16 rsvd1:1; // 2
Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC
Uint16 rsvd2:4; // 7:4 reserved
Uint16 SPIENCLK:1; // 8 Enable low speed clk to SPI
Uint16 rsvd3:1; // 9 reserved
Uint16 SCIENCLKA:1; // 10 Enable low speed clk to SCI-A
Uint16 SCIENCLKB:1; // 11 Enable low speed clk to SCI-B
Uint16 MCBSPENCLK:1; // 12 Enable low speed clk to McBSP
Uint16 rsvd4:1; // 13 reserved
Uint16 ECANENCLK:1; // 14 Enable system clk to eCAN
};
union PCLKCR_REG {
Uint16 all;
struct PCLKCR_BITS bit;
};
// System control and status register bit definitions:
struct SCSR_BITS { // bits description
Uint16 WDOVERRIDE:1; // 0 Allow watchdog disable
Uint16 WDENINT:1; // 1 Enable/disable WD interrupt
Uint16 rsvd1:14; // 15:2 reserved
};
union SCSR_REG {
Uint16 all;
struct SCSR_BITS bit;
};
//---------------------------------------------------------------------------
// System Control Register File:
//
struct SYS_CTRL_REGS {
Uint16 rsvd1[10]; // 0-9
union HISPCP_REG HISPCP; // 10: High-speed peripheral clock pre-scaler
union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler
union PCLKCR_REG PCLKCR; // 12: Peripheral clock control register
Uint16 rsvd2; // 13
Uint16 LPMCR0; // 14: Low-power mode control register 0
Uint16 LPMCR1; // 15: Low-power mode control register 1
Uint16 rsvd3; // 16
Uint16 PLLCR; // 17: PLL control register
union SCSR_REG SCSR; // 18: System control and status register
Uint16 WDCNTR; // 19: WD counter register
Uint16 rsvd4; // 20
Uint16 WDKEY; // 21: WD reset key register
Uint16 rsvd5[3]; // 22-24
Uint16 WDCR; // 25: WD timer control register
Uint16 rsvd6[6]; // 26-31
};
/* --------------------------------------------------- */
/* CSM Registers */
/* */
/* ----------------------------------------------------*/
/* CSM Status & Control register bit definitions */
struct CSMSCR_BITS { // bit description
Uint16 SECURE:1; // 0 Secure flag
Uint16 rsvd1:14; // 14-1 reserved
Uint16 FORCESEC:1; // 15 Force Secure control bit
};
/* Allow access to the bit fields or entire register */
union CSMSCR_REG {
Uint16 all;
struct CSMSCR_BITS bit;
};
/* CSM Register File */
struct CSM_REGS {
Uint16 KEY0; // KEY reg bits 15-0
Uint16 KEY1; // KEY reg bits 31-16
Uint16 KEY2; // KEY reg bits 47-32
Uint16 KEY3; // KEY reg bits 63-48
Uint16 KEY4; // KEY reg bits 79-64
Uint16 KEY5; // KEY reg bits 95-80
Uint16 KEY6; // KEY reg bits 111-96
Uint16 KEY7; // KEY reg bits 127-112
Uint16 rsvd1; // reserved
Uint16 rsvd2; // reserved
Uint16 rsvd3; // reserved
Uint16 rsvd4; // reserved
Uint16 rsvd5; // reserved
Uint16 rsvd6; // reserved
Uint16 rsvd7; // reserved
union CSMSCR_REG CSMSCR; // CSM Status & Control register
};
/* Password locations */
struct CSM_PWL {
Uint16 PSWD0; // PSWD bits 15-0
Uint16 PSWD1; // PSWD bits 31-16
Uint16 PSWD2; // PSWD bits 47-32
Uint16 PSWD3; // PSWD bits 63-48
Uint16 PSWD4; // PSWD bits 79-64
Uint16 PSWD5; // PSWD bits 95-80
Uint16 PSWD6; // PSWD bits 111-96
Uint16 PSWD7; // PSWD bits 127-112
};
/* Flash Registers */
/* Flash Option Register bit definitions */
struct FOPT_BITS { // bit description
Uint16 ENPIPE:1; // 0 Enable Pipeline Mode
Uint16 rsvd:15; // 1-15 reserved
};
/* Allow access to the bit fields or entire register */
union FOPT_REG {
Uint16 all;
struct FOPT_BITS bit;
};
/* Flash Power Modes Register bit definitions */
struct FPWR_BITS { // bit description
Uint16 PWR:2; // 0-1 Power Mode bits
Uint16 rsvd:14; // 2-15 reserved
};
/* Allow access to the bit fields or entire register */
union FPWR_REG {
Uint16 all;
struct FPWR_BITS bit;
};
/* Flash Status Register bit definitions */
struct FSTATUS_BITS { // bit description
Uint16 PWRS:2; // 0-1 Power Mode Status bits
Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits
Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits
Uint16 rsvd1:4; // 4-7 reserved
Uint16 V3STAT:1; // 8 VDD3V Status Latch bit
Uint16 rsvd2:7; // 9-15 reserved
};
/* Allow access to the bit fields or entire register */
union FSTATUS_REG {
Uint16 all;
struct FSTATUS_BITS bit;
};
/* Flash Sleep to Standby Wait Counter Register bit definitions */
struct FSTDBYWAIT_BITS { // bit description
Uint16 STDBYWAIT:8; // 0-7 Bank/Pump Sleep to Standby Wait Count bits
Uint16 rsvd:8; // 8-15 reserved
};
/* Allow access to the bit fields or entire register */
union FSTDBYWAIT_REG {
Uint16 all;
struct FSTDBYWAIT_BITS bit;
};
/* Flash Standby to Active Wait Counter Register bit definitions */
struct FACTIVEWAIT_BITS { // bit description
Uint16 ACTIVEWAIT:8; // 0-7 Bank/Pump Standby to Active Wait Count bits
Uint16 rsvd:8; // 8-15 reserved
};
/* Allow access to the bit fields or entire register */
union FACTIVEWAIT_REG {
Uint16 all;
struct FACTIVEWAIT_BITS bit;
};
/* Bank Read Access Wait State Register bit definitions */
struct FBANKWAIT_BITS { // bit description
Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits
Uint16 rsvd1:4; // 4-7 reserved
Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits
Uint16 rsvd2:4; // 12-15 reserved
};
/* Allow access to the bit fields or entire register */
union FBANKWAIT_REG {
Uint16 all;
struct FBANKWAIT_BITS bit;
};
/* OTP Read Access Wait State Register bit definitions */
struct FOTPWAIT_BITS { // bit description
Uint16 OPTWAIT:5; // 0-4 OTP Read Wait State bits
Uint16 rsvd:11; // 5-15 reserved
};
/* Allow access to the bit fields or entire register */
union FOTPWAIT_REG {
Uint16 all;
struct FOTPWAIT_BITS bit;
};
struct FLASH_REGS {
union FOPT_REG FOPT; // Option Register
Uint16 rsvd1; // reserved
union FPWR_REG FPWR; // Power Modes Register
union FSTATUS_REG FSTATUS; // Status Register
union FSTDBYWAIT_REG FSTDBYWAIT; // Pump/Bank Sleep to Standby Wait State Register
union FACTIVEWAIT_REG FACTIVEWAIT; // Pump/Bank Standby to Active Wait State Register
union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register
union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register
};
//---------------------------------------------------------------------------
// System Control External References & Function Declarations:
//
extern volatile struct SYS_CTRL_REGS SysCtrlRegs;
extern volatile struct CSM_REGS CsmRegs;
extern volatile struct CSM_PWL CsmPwl;
extern volatile struct FLASH_REGS FlashRegs;
#endif // end of DSP28_SYS_CTRL_H definition
#ifndef DSP28_EV_H
#define DSP28_EV_H
/* Overall Timer Control Register */
struct GPTCONA_BITS {
Uint16 T1PIN:2; // 1:0 Polarity of GP timer 1 compare
Uint16 T2PIN:2; // 3:2 Polarity of GP timer 2 compare
Uint16 rsvd1:2; // 5:4 reserved
Uint16 TCOMPOE:1; // 6 Compare output enable
Uint16 T1TOADC:2; // 8:7 Start ADC with timer 1 event
Uint16 T2TOADC:2; // 10:9 Start ADC with timer 2 event
Uint16 rsvd2:2; // 12:11 reserved
Uint16 T1STAT:1; // 13 GP Timer 1 status (read only)
Uint16 T2STAT:1; // 14 GP Timer 2 status (read only)
Uint16 rsvd:1; // 15 reserved
};
/* Allow access to the bit fields or entire register */
union GPTCONA_REG {
Uint16 all;
struct GPTCONA_BITS bit;
};
struct GPTCONB_BITS {
Uint16 T3PIN:2; // 1:0 Polarity of GP timer 3 compare
Uint16 T4PIN:2; // 3:2 Polarity of GP timer 4 compare
Uint16 T1CMPOE:1; // 4 Timer1 compare output
Uint16 T2CMPOE:1; // 5 Timer2 compare output
Uint16 TCOMPOE:1; // 6 Compare output enable
Uint16 T3TOADC:2; // 8:7 Start ADC with timer 3 event
Uint16 T4TOADC:2; // 10:9 Start ADC with timer 4 event
Uint16 T1CTRIP:1; // 11 Timer1 trip enable
Uint16 T2CTRIP:1; // 12 Timer2 trip enable
Uint16 T3STAT:1; // 13 GP Timer 3 status (read only)
Uint16 T4STAT:1; // 14 GP Timer 4 status (read only)
Uint16 rsvd:1; // 15 reserved
};
/* Allow access to the bit fields or entire register */
union GPTCONB_REG {
Uint16 all;
struct GPTCONB_BITS bit;
};
/* Timer Control Register bit defintions */
struct TCONA_BITS {
Uint16 SET1PR:1; // 0 Period register select
Uint16 TECMPR:1; // 1 Timer compare enable
Uint16 TCLD10:2; // 3:2 Timer copare register reload
Uint16 TCLKS10:2; // 5:4 Clock source select
Uint16 TENABLE:1; // 6 Timer enable
Uint16 T2SWT1:1; // 7 Start GP timer 2 with GP timer 1's enable
Uint16 TPS:3; // 10:8 Input clock prescaler
Uint16 TMODE:2; // 12:11 Count mode selection
Uint16 rsvd:1; // 13 reserved
Uint16 FREE:1; // 14 Free emulation control
Uint16 SOFT:1; // 15 Soft emulation control
};
/* Allow access to the bit fields or entire register */
union TCONA_REG {
Uint16 all;
struct TCONA_BITS bit;
};
struct TCONB_BITS {
Uint16 SET3PR:1; // 0 Period register select
Uint16 TECMPR:1; // 1 Timer compare enable
Uint16 TCLD10:2; // 3:2 Timer copare register reload
Uint16 TCLKS10:2; // 5:4 Clock source select
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