📄 dsp28_device.h
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//
// TMDX ALPHA RELEASE
// Intended for product evaluation purposes
//
//###########################################################################
//
// FILE: DSP28_Device.h
//
// TITLE: DSP28 Device Definitions.
//
//###########################################################################
//
// Ver | dd mmm yyyy | Who | Description of changes
// =====|=============|======|===============================================
// 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
// 0.56| 20 May 2002 | L.H. | No change
// 0.57| 24 May 2002 | L.H. | Added generic BIT# #define statements
//###########################################################################
#ifndef DSP28_DEVICE_H
#define DSP28_DEVICE_H
#define TARGET 1
//---------------------------------------------------------------------------
// User To Select Target Device:
#define F2812 TARGET
#define F2810 0
//---------------------------------------------------------------------------
// Common CPU Definitions:
//
extern cregister volatile unsigned int IFR;
extern cregister volatile unsigned int IER;
#define EINT asm(" clrc INTM")
#define DINT asm(" setc INTM")
#define ERTM asm(" clrc DBGM")
#define DRTM asm(" setc DBGM")
#define EALLOW asm(" EALLOW")
#define EDIS asm(" EDIS")
#define ESTOP0 asm(" ESTOP0")
#define NOP asm(" NOP")
#define M_INT1 0x0001
#define M_INT2 0x0002
#define M_INT3 0x0004
#define M_INT4 0x0008
#define M_INT5 0x0010
#define M_INT6 0x0020
#define M_INT7 0x0040
#define M_INT8 0x0080
#define M_INT9 0x0100
#define M_INT10 0x0200
#define M_INT11 0x0400
#define M_INT12 0x0800
#define M_INT13 0x1000
#define M_INT14 0x2000
#define M_DLOG 0x4000
#define M_RTOS 0x8000
#define BIT0 0x0001
#define BIT1 0x0002
#define BIT2 0x0004
#define BIT3 0x0008
#define BIT4 0x0010
#define BIT5 0x0020
#define BIT6 0x0040
#define BIT7 0x0080
#define BIT8 0x0100
#define BIT9 0x0200
#define BIT10 0x0400
#define BIT11 0x0800
#define BIT12 0x1000
#define BIT13 0x2000
#define BIT14 0x4000
#define BIT15 0x8000
//---------------------------------------------------------------------------
// For Portability, User Is Recommended To Use Following Data Type Size
// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers:
//
typedef int int16;
typedef long int32;
typedef unsigned int Uint16;
typedef unsigned long Uint32;
//---------------------------------------------------------------------------
// Include All Peripheral Header Files:
//
#include "DSP28_DefaultIsr.h" // Software Prioritization for PIE Interrupts
//---------------------------------------------------------------------------
// Define Device Init Function Prototype:
//
#endif // end of DSP28_DEVICE_H definition
#ifndef EXAMPLE_H
#define EXAMPLE_H
/*---- shared global function prototypes -----------------------------------*/
extern void InitAdc(void);
extern void InitPieCtrl(void);
extern void InitPieVectTable(void);
extern void InitSysCtrl(void);
extern void KickDog(void);
extern void InitEva(void);
#endif // - end of EXAMPLE_H
#ifndef DSP28_DEV_EMU_H
#define DSP28_DEV_EMU_H
//---------------------------------------------------------------------------
// Device Emulation Register Bit Definitions:
//
// Device Configuration Register Bit Definitions
struct DEVICECNF_BITS { // bits description
Uint16 rsvd1:3; // 2:0 reserved
Uint16 VMAPS:1; // 3 VMAP Status
Uint16 rsvd2:1; // 4 reserved
Uint16 XRSn:1; // 5 XRSn Signal Status
Uint16 rsvd3:10; // 15:6
Uint16 rsvd4:3; // 18:6
Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection
Uint16 rsvd5:12; // 31:20 reserved
};
union DEVICECNF_REG {
Uint32 all;
struct DEVICECNF_BITS bit;
};
// Device ID Register Bit Definitions
struct DEVICEID_BITS { // bits description
Uint16 PARTID:16; // 15:0 Part ID
Uint16 REVID:16; // 31:16 Revision
};
union DEVICEID_REG {
Uint32 all;
struct DEVICEID_BITS bit;
};
struct DEV_EMU_REGS {
union DEVICECNF_REG DEVICECNF;
union DEVICEID_REG DEVICEID;
Uint16 PROTSTART;
Uint16 PROTRANGE;
Uint16 rsvd[202];
Uint16 M0RAMDFT;
Uint16 M1RAMDFT;
Uint16 L0RAMDFT;
Uint16 L1RAMDFT;
Uint16 H0RAMDFT;
};
//---------------------------------------------------------------------------
// Device Emulation Register References & Function Declarations:
//
extern volatile struct DEV_EMU_REGS DevEmuRegs;
#endif // end of DSP28_DEV_EMU_H definition
#ifndef DSP28_PIE_CTRL_H
#define DSP28_PIE_CTRL_H
//---------------------------------------------------------------------------
// PIE Control Register Bit Definitions:
//
// PIECTRL: Register bit definitions:
struct PIECTRL_BITS { // bits description
Uint16 ENPIE:1; // 0 Enable PIE block
Uint16 PIEVECT:15; // 15:1 Fetched vector address
};
union PIECTRL_REG {
Uint16 all;
struct PIECTRL_BITS bit;
};
// PIEIER: Register bit definitions:
struct PIEIER_BITS { // bits description
Uint16 INTx1:1; // 0 INTx.1
Uint16 INTx2:1; // 1 INTx.2
Uint16 INTx3:1; // 2 INTx.3
Uint16 INTx4:1; // 3 INTx.4
Uint16 INTx5:1; // 4 INTx.5
Uint16 INTx6:1; // 5 INTx.6
Uint16 INTx7:1; // 6 INTx.7
Uint16 INTx8:1; // 7 INTx.8
Uint16 rsvd:8; // 15:8 reserved
};
union PIEIER_REG {
Uint16 all;
struct PIEIER_BITS bit;
};
// PIEIFR: Register bit definitions:
struct PIEIFR_BITS { // bits description
Uint16 INTx1:1; // 0 INTx.1
Uint16 INTx2:1; // 1 INTx.2
Uint16 INTx3:1; // 2 INTx.3
Uint16 INTx4:1; // 3 INTx.4
Uint16 INTx5:1; // 4 INTx.5
Uint16 INTx6:1; // 5 INTx.6
Uint16 INTx7:1; // 6 INTx.7
Uint16 INTx8:1; // 7 INTx.8
Uint16 rsvd:8; // 15:8 reserved
};
union PIEIFR_REG {
Uint16 all;
struct PIEIFR_BITS bit;
};
// PIEACK: Register bit definitions:
struct PIEACK_BITS { // bits description
Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1
Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2
Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3
Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4
Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5
Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6
Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7
Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8
Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9
Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10
Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11
Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12
Uint16 rsvd:4; // 15:12 reserved
};
union PIEACK_REG {
Uint16 all;
struct PIEACK_BITS bit;
};
//---------------------------------------------------------------------------
// PIE Control Register File:
//
struct PIE_CTRL_REGS {
union PIECTRL_REG PIECRTL; // PIE control register
union PIEACK_REG PIEACK; // PIE acknowledge
union PIEIER_REG PIEIER1; // PIE INT1 IER register
union PIEIFR_REG PIEIFR1; // PIE INT1 IFR register
union PIEIER_REG PIEIER2; // PIE INT2 IER register
union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register
union PIEIER_REG PIEIER3; // PIE INT3 IER register
union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register
union PIEIER_REG PIEIER4; // PIE INT4 IER register
union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register
union PIEIER_REG PIEIER5; // PIE INT5 IER register
union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register
union PIEIER_REG PIEIER6; // PIE INT6 IER register
union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register
union PIEIER_REG PIEIER7; // PIE INT7 IER register
union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register
union PIEIER_REG PIEIER8; // PIE INT8 IER register
union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register
union PIEIER_REG PIEIER9; // PIE INT9 IER register
union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register
union PIEIER_REG PIEIER10; // PIE INT10 IER register
union PIEIFR_REG PIEIFR10; // PIE INT10 IFR register
union PIEIER_REG PIEIER11; // PIE INT11 IER register
union PIEIFR_REG PIEIFR11; // PIE INT11 IFR register
union PIEIER_REG PIEIER12; // PIE INT12 IER register
union PIEIFR_REG PIEIFR12; // PIE INT12 IFR register
};
#define PIEACK_GROUP1 0x0001;
#define PIEACK_GROUP2 0x0002;
#define PIEACK_GROUP3 0x0004;
#define PIEACK_GROUP4 0x0008;
#define PIEACK_GROUP5 0x0010;
#define PIEACK_GROUP6 0x0020;
#define PIEACK_GROUP7 0x0040;
#define PIEACK_GROUP8 0x0080;
#define PIEACK_GROUP9 0x0100;
#define PIEACK_GROUP10 0x0200;
#define PIEACK_GROUP11 0x0400;
#define PIEACK_GROUP12 0x0800;
//---------------------------------------------------------------------------
// PIE Control Registers External References & Function Declarations:
//
extern volatile struct PIE_CTRL_REGS PieCtrl;
#endif // end of DSP28_PIE_CTRL_H definition
#ifndef DSP28_PIE_VECT_H
#define DSP28_PIE_VECT_H
//---------------------------------------------------------------------------
// PIE Interrupt Vector Table Definition:
//
// Create a user type called PINT (pointer to interrupt):
typedef interrupt void(*PINT)(void);
// Define Vector Table:
struct PIE_VECT_TABLE {
// Reset is never fetched from this table.
// It will always be fetched from 0x3FFFC0 in either
// boot ROM or XINTF Zone 7 depending on the state of
// the XMP/MC input signal. On the F2810 it is always
// fetched from boot ROM.
PINT PIE1_RESERVED;
PINT PIE2_RESERVED;
PINT PIE3_RESERVED;
PINT PIE4_RESERVED;
PINT PIE5_RESERVED;
PINT PIE6_RESERVED;
PINT PIE7_RESERVED;
PINT PIE8_RESERVED;
PINT PIE9_RESERVED;
PINT PIE10_RESERVED;
PINT PIE11_RESERVED;
PINT PIE12_RESERVED;
PINT PIE13_RESERVED;
// Non-Peripheral Interrupts:
PINT XINT13; // XINT13
PINT TINT2; // CPU-Timer2
PINT DATALOG; // Datalogging interrupt
PINT RTOSINT; // RTOS interrupt
PINT EMUINT; // Emulation interrupt
PINT XNMI; // Non-maskable interrupt
PINT ILLEGAL; // Illegal operation TRAP
PINT USER0; // User Defined trap 0
PINT USER1; // User Defined trap 1
PINT USER2; // User Defined trap 2
PINT USER3; // User Defined trap 3
PINT USER4; // User Defined trap 4
PINT USER5; // User Defined trap 5
PINT USER6; // User Defined trap 6
PINT USER7; // User Defined trap 7
PINT USER8; // User Defined trap 8
PINT USER9; // User Defined trap 9
PINT USER10; // User Defined trap 10
PINT USER11; // User Defined trap 11
// Group 1 PIE Peripheral Vectors:
PINT PDPINTA; // EV-A
PINT PDPINTB; // EV-B
PINT rsvd1_3;
PINT XINT1;
PINT XINT2;
PINT ADCINT; // ADC
PINT TINT0; // Timer 0
PINT WAKEINT; // WD
// Group 2 PIE Peripheral Vectors:
PINT CMP1INT; // EV-A
PINT CMP2INT; // EV-A
PINT CMP3INT; // EV-A
PINT T1PINT; // EV-A
PINT T1CINT; // EV-A
PINT T1UFINT; // EV-A
PINT T1OFINT; // EV-A
PINT rsvd2_8;
// Group 3 PIE Peripheral Vectors:
PINT T2PINT; // EV-A
PINT T2CINT; // EV-A
PINT T2UFINT; // EV-A
PINT T2OFINT; // EV-A
PINT CAPINT1; // EV-A
PINT CAPINT2; // EV-A
PINT CAPINT3; // EV-A
PINT rsvd3_8;
// Group 4 PIE Peripheral Vectors:
PINT CMP4INT; // EV-B
PINT CMP5INT; // EV-B
PINT CMP6INT; // EV-B
PINT T3PINT; // EV-B
PINT T3CINT; // EV-B
PINT T3UFINT; // EV-B
PINT T3OFINT; // EV-B
PINT rsvd4_8;
// Group 5 PIE Peripheral Vectors:
PINT T4PINT; // EV-B
PINT T4CINT; // EV-B
PINT T4UFINT; // EV-B
PINT T4OFINT; // EV-B
PINT CAPINT4; // EV-B
PINT CAPINT5; // EV-B
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