registermap.h

5509的代码程序

;外设总线控制器配置寄存器
CMR	.set	0x0000
ICR	.set	0x0001
ISTR	.set	0x0002
B00T_MOD	.set	0x000F
;外部存储器接口(EMIF)寄存器
EGCR	.set	0x0800
EMI_RST	.set	0x0801
EMI_BE	.set	0x0802

CE0_1	.set	0x0803
CE0_2	.set	0x0804
CE0_3	.set	0x0805

CE1_1	.set	0x0806
CE1_2	.set	0x0807
CE1_3	.set	0x0808

CE2_1	.set	0x0809
CE2_2	.set	0x080A
CE2_3	.set	0x080B

CE3_1	.set	0x080C
CE3_2	.set	0x080D
CE3_3	.set	0x080E

SDC1	.set	0x080F
SDPER	.set	0x0810
SDCNT	.set	0x0811
INIT	.set	0x0812
SDC2	.set	0x0813

;DMA配置寄存器
;通道0
DMA_CSDP0	.set	0X0C00
DMA_CCR0	.set	0X0C01
DMA_CICR0	.set	0X0C02
DMA_CSR0	.set	0X0C03
DMA_CSSA_L0	.set	0X0C04
DMA_CSSA_U0	.set	0X0C05
DMA_CDSA_L0	.set	0X0C06
DMA_CDSA_U0	.set	0X0C07
DMA_CEN0	.set	0X0C08
DMA_CFN0	.set	0X0C09
DMA_CFI0	.set	0X0C0A
DMA_CEI0	.set	0X0C0B

;通道1
DMA_CSDP1	.set	0X0C20
DMA_CCR1	.set	0X0C21
DMA_CICR1	.set	0X0C22
DMA_CSR1	.set	0X0C23
DMA_CSSA_L1	.set	0X0C24
DMA_CSSA_U1	.set	0X0C25
DMA_CDSA_L1	.set	0X0C26
DMA_CDSA_U1	.set	0X0C27
DMA_CEN1	.set	0X0C28
DMA_CFN1	.set	0X0C29
DMA_CFI1	.set	0X0C2A
DMA_CEI1	.set	0X0C2B

;通道2
DMA_CSDP2	.set	0X0C40
DMA_CCR2	.set	0X0C41
DMA_CICR2	.set	0X0C42
DMA_CSR2	.set	0X0C43
DMA_CSSA_L2	.set	0X0C44
DMA_CSSA_U2	.set	0X0C45
DMA_CDSA_L2	.set	0X0C46
DMA_CDSA_U2	.set	0X0C47
DMA_CEN2	.set	0X0C48
DMA_CFN2	.set	0X0C49
DMA_CFI2	.set	0X0C4A
DMA_CEI2	.set	0X0C4B

;通道3
DMA_CSDP3	.set	0X0C60
DMA_CCR3	.set	0X0C61
DMA_CICR3	.set	0X0C62
DMA_CSR3	.set	0X0C63
DMA_CSSA_L3	.set	0X0C64
DMA_CSSA_U3	.set	0X0C65
DMA_CDSA_L3	.set	0X0C66
DMA_CDSA_U3	.set	0X0C67
DMA_CEN3	.set	0X0C68
DMA_CFN3	.set	0X0C69
DMA_CFI3	.set	0X0C6A
DMA_CEI3	.set	0X0C6B

;通道4
DMA_CSDP4	.set	0X0C80
DMA_CCR4	.set	0X0C81
DMA_CICR4	.set	0X0C82
DMA_CSR4	.set	0X0C83
DMA_CSSA_L4	.set	0X0C84
DMA_CSSA_U4	.set	0X0C85
DMA_CDSA_L4	.set	0X0C86
DMA_CDSA_U4	.set	0X0C87
DMA_CEN4	.set	0X0C88
DMA_CFN4	.set	0X0C89
DMA_CFI4	.set	0X0C8A
DMA_CEI4	.set	0X0C8B

;通道5
DMA_CSDP5	.set	0X0CA0
DMA_CCR5	.set	0X0CA1
DMA_CICR5	.set	0X0CA2
DMA_CSR5	.set	0X0CA3
DMA_CSSA_L5	.set	0X0CA4
DMA_CSSA_U5	.set	0X0CA5
DMA_CDSA_L5	.set	0X0CA6
DMA_CDSA_U5	.set	0X0CA7
DMA_CEN5	.set	0X0CA8
DMA_CFN5	.set	0X0CA9
DMA_CFI5	.set	0X0CAA
DMA_CEI5	.set	0X0CAB
DMA_GCR		.set	0X0E00

;定时器0
TIM0	.set	0x1000
PRD0	.set	0x1001
TCR0	.set	0x1002
PRSC0	.set	0x1003

;指令缓冲寄存器
ICGC	.set	0x1400
ICFL0	.set	0x1401
ICFL1	.set	0x1402
ICWC	.set	0x1403
ICRC1	.set	0x1404
ICRTAG1	.set	0x1405
ICRC2	.set	0x1406
ICRTAG2	.set	0x1407

;时钟发生器
CLKMD	.set	0x1c00

;定时器1
TIM1	.set	0x2400
PRD1	.set	0x2401
TCR1	.set	0x2402
PRSC1	.set	0x2403

;GPIDO
IODIR	.set	0x3400
IODATA	.set	0x3401


DRR2_0	.set	0x2800		;Data Recieve Register 2
DRR1_0	.set 	0x2801      ;Data Recieve Register 1
DXR2_0	.set	0x2802      ;Data Transmit Register 2
DXR1_0	.set 	0x2803		;Data Transmit Register 1 

SPCR2_0	.set	0x2804      ;Serial Port Control Register 2
SPCR1_0	.set	0x2805		;Serial Port Control Register 1

RCR2_0	.set	0x2806      ;Recieve Control Register 2
RCR1_0	.set	0x2807		;Recieve Control Register 1 

XCR2_0	.set	0x2808      ;Transmit Control Register 2
XCR1_0	.set	0x2809		;Transmit Control Register 1

SRGR2_0	.set	0x280A      ;Sample Rate Generator Register 2
SRGR1_0	.set	0x280B		;Sample Rate Generator Register 1

MCR2_0	.set	0x280C      ;Multi-Channel Register 2
MCR1_0	.set	0x280D		;Multi-Channel Register 1

RCERA_0	.set	0x280E      ;Recieve Channel Enable Register A
RCERB_0	.set	0x280F		;Recieve Channel Enable Register B

XCERA_0	.set	0x2810      ;Transmit Channel Enable Register A
XCERB_0	.set	0x2811		;Transmit Channel Enable Register B 

PCR_0   .set	0x2812		;Pin Control Register

RCERC_0	.set	0x2813      ;Recieve Channel Enable Register C
RCERD_0	.set	0x2814		;Recieve Channel Enable Register D
 
XCERC_0	.set	0x2815      ;Transmit Channel Enable Register C
XCERD_0	.set	0x2816		;Transmit Channel Enable Register D

RCERE_0	.set	0x2817      ;Recieve Channel Enable Register E
RCERF_0	.set	0x2818		;Recieve Channel Enable Register F

XCERE_0	.set	0x2819      ;Transmit Channel Enable Register E
XCERF_0	.set	0x281A		;Transmit Channel Enable Register F

RCERG_0	.set	0x281B      ;Recieve Channel Enable Register G
RCERH_0	.set	0x281C		;Recieve Channel Enable Register H

XCERG_0	.set	0x281D      ;Transmit Channel Enable Register G
XCERH_0	.set	0x281E		;Transmit Channel Enable Register H

** McBSP 1 Register Address **
DRR2_1	.set	0x2C00		;Data Recieve Register 2
DRR1_1	.set 	0x2C01      ;Data Recieve Register 1
DXR2_1	.set	0x2C02      ;Data Transmit Register 2
DXR1_1	.set 	0x2C03		;Data Transmit Register 1 

SPCR2_1	.set	0x2C04      ;Serial Port Control Register 2
SPCR1_1	.set	0x2C05		;Serial Port Control Register 1

RCR2_1	.set	0x2C06      ;Recieve Control Register 2
RCR1_1	.set	0x2C07		;Recieve Control Register 1 

XCR2_1	.set	0x2C08      ;Transmit Control Register 2
XCR1_1	.set	0x2C09		;Transmit Control Register 1

SRGR2_1	.set	0x2C0A      ;Sample Rate Generator Register 2
SRGR1_1	.set	0x2C0B		;Sample Rate Generator Register 1

MCR2_1	.set	0x2C0C      ;Multi-Channel Register 2
MCR1_1	.set	0x2C0D		;Multi-Channel Register 1

RCERA_1	.set	0x2C0E      ;Recieve Channel Enable Register A
RCERB_1	.set	0x2C0F		;Recieve Channel Enable Register B

XCERA_1	.set	0x2C10      ;Transmit Channel Enable Register A
XCERB_1	.set	0x2C11		;Transmit Channel Enable Register B 

PCR_1   .set	0x2C12		;Pin Control Register

RCERC_1	.set	0x2C13      ;Recieve Channel Enable Register C
RCERD_1	.set	0x2C14		;Recieve Channel Enable Register D
 
XCERC_1	.set	0x2C15      ;Transmit Channel Enable Register C
XCERD_1	.set	0x2C16		;Transmit Channel Enable Register D

RCERE_1	.set	0x2C17      ;Recieve Channel Enable Register E
RCERF_1	.set	0x2C18		;Recieve Channel Enable Register F

XCERE_1	.set	0x2C19      ;Transmit Channel Enable Register E
XCERF_1	.set	0x2C1A		;Transmit Channel Enable Register F

RCERG_1	.set	0x2C1B      ;Recieve Channel Enable Register G
RCERH_1	.set	0x2C1C		;Recieve Channel Enable Register H

XCERG_1	.set	0x2C1D      ;Transmit Channel Enable Register G
XCERH_1	.set	0x2C1E		;Transmit Channel Enable Register H

** McBSP 2 Register Address **
DRR2_2	.set	0x3000		;Data Recieve Register 2
DRR1_2	.set 	0x3001      ;Data Recieve Register 1
DXR2_2	.set	0x3002      ;Data Transmit Register 2
DXR1_2	.set 	0x3003		;Data Transmit Register 1 

SPCR2_2	.set	0x3004      ;Serial Port Control Register 2
SPCR1_2	.set	0x3005		;Serial Port Control Register 1

RCR2_2	.set	0x3006      ;Recieve Control Register 2
RCR1_2	.set	0x3007		;Recieve Control Register 1 

XCR2_2	.set	0x3008      ;Transmit Control Register 2
XCR1_2	.set	0x3009		;Transmit Control Register 1

SRGR2_2	.set	0x300A      ;Sample Rate Generator Register 2
SRGR1_2	.set	0x300B		;Sample Rate Generator Register 1

MCR2_2	.set	0x300C      ;Multi-Channel Register 2
MCR1_2	.set	0x300D		;Multi-Channel Register 1

RCERA_2	.set	0x300E      ;Recieve Channel Enable Register A
RCERB_2	.set	0x300F		;Recieve Channel Enable Register B

XCERA_2	.set	0x3010      ;Transmit Channel Enable Register A
XCERB_2	.set	0x3011		;Transmit Channel Enable Register B 

PCR_2   .set	0x3012		;Pin Control Register

RCERC_2	.set	0x3013      ;Recieve Channel Enable Register C
RCERD_2	.set	0x3014		;Recieve Channel Enable Register D
 
XCERC_2	.set	0x3015      ;Transmit Channel Enable Register C
XCERD_2	.set	0x3016		;Transmit Channel Enable Register D

RCERE_2	.set	0x3017      ;Recieve Channel Enable Register E
RCERF_2	.set	0x3018		;Recieve Channel Enable Register F

XCERE_2	.set	0x3019      ;Transmit Channel Enable Register E
XCERF_2	.set	0x301A		;Transmit Channel Enable Register F

RCERG_2	.set	0x301B      ;Recieve Channel Enable Register G
RCERH_2	.set	0x301C		;Recieve Channel Enable Register H

XCERG_2	.set	0x301D      ;Transmit Channel Enable Register G
XCERH_2	.set	0x301E		;Transmit Channel Enable Register H

;外部总线选择寄存器
EBSR	.set	0x6C00