📄 t101_util.lst
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206 0x19 , 0x07, //YCbCr_SW_REG
207 //Enable CSC
208 0x91 , 0x00, //BTIN_PATTERN_REG
209 //DSP Clock
210 #ifdef SEQ_MODE // For sequential mode, bruce, 2006/01/09
0xCB , (CPH1_PH | PHASE_DIV),
0xCC , (CPH3_PH | CPH2_PH),
0xC8 , DFDIV_S,
0xC9 , DIDIV_S,
0xCA , DODIV_S,
#else
217 0xC8 , DFDIV_40, //PLLDIV_F
218 0xC9 , DIDIV, //PLLDIV_I
219 #endif
220 //DSP Colck Polarity
221 0xC1 , 0xc8, //POUT_CTRL3_REG
222 //H&V Main Display Pixel Clock Setted
223 0xDC ,(H_Size&0xFF),//H Size //HMDISP_SIZE_L_REG
224 0xDD ,(H_Size>>8), //HMDISP_SIZE_H_REG
225 0xDE ,(V_Size&0xFF),//V Size //20 //VMDISP_SIZE_L_REG
226 0xDF ,(V_Size>>8), //VMDISP_SIZE_H_REG
227 //H&V Display Pixel Clock Setted
228
229 #ifdef _160_234
0xcb , 0x66,
0xcc , 0x42,
0x79 , 0x0d,
#endif
234 0xB0 , DISP_DFLT_HDENS, //H Start //DWHS_L_REG
235 0xB1 ,(DISP_DFLT_HDENS>>8), //DWHS_H_REG
236 0xB2 , DISP_DFLT_VDENS, //V Start //DWVS_L_REG
237 0xB3 ,(DISP_DFLT_VDENS>>8), //25 //DWVS_H_REG
238 0xB4 ,(H_Size&0xFF), //H Width //DWHSZ_L_REG
239 0xB5 ,(H_Size>>8), //DWHSZ_H_REG
240 0xB6 ,(V_Size&0xFF), //DWVSZ_L_REG
C51 COMPILER V7.50 T101_UTIL 01/12/2006 13:31:12 PAGE 5
241 0xB7 ,(V_Size>>8), //DWVSZ_H_REG
242 0xB8 , DISP_DFLT_HTOTAL, //H Total //30 //PH_TOT_L_REG
243 0xB9 ,(DISP_DFLT_HTOTAL>>8), //PH_TOT_H_REG
244 0xBA , DISP_DFLT_VTOTAL, //V Total //PV_TOT_L_REG
245 0xBB ,(DISP_DFLT_VTOTAL>>8), //PV_TOT_H_REG
246 0xBC , DISP_DFLT_HSWIDTH, //HSYNC Width //PH_PW_L_REG
247 0xBD ,(DISP_DFLT_HSWIDTH>>8), //35 //PH_PW_H_REG
248 0xBE , DISP_DFLT_VSWIDTH, //VSYNC Width //PV_PW_L_REG
249 0xBF ,(DISP_DFLT_VSWIDTH>>8), //PV_PW_H_REG
250 //Scaling
251 0x72 , 0x33, //H Scale //SC_HOR_H1
252 0x73 , 0x73, //SC_HOR_H2
253 0x74 , 0x00, //V Scale //40 //SC_VER_V1
254 0x75 , 0x40, //SC_VER_V2
255 //LineBuffer Prefill
256 0x84 , 0x00, //LINE_BUF_L_REG
257 0x85 , 0x10, //LINE_BUF_H_REG
258 0xE1 , 0xa0, //OPIN_CFG_REG
259 0x50 , 0x10, //45 //VSYNC_TIME_MEA_REG
260 0x38 , 0x50, //HSYNC_MISSCNT_L_REG
261 0x39 , 0x00, //HSYNC_MISSCNT_H_REG
262 0x3A , 0x20, //VSYNC_DLT_REG
263 0x3B , 0x03, //HSYNC_DLT_REG
264 #ifdef TCON
265 0xE0 , (0x91 | CPH1 | CPH2 |CPH3), //PW_MGRCTRL_REG, Bruce, 2006/01/09 for flexibility
266 #ifdef T100
0xE1 , 0xf4, //OPIN_CFG_REG
#else
269 0xe1 , 0xe0,
270 #ifdef _160_234
0xe0 , 0xbf,
#endif
273 #endif
274 #else
0xE0 , (0x91 | CPH1 | CPH2 |CPH3), //PW_MGRCTRL_REG
0xE1 , 0x00, //OPIN_CFG_REG
#endif
278 0x9C , 0x02, //DITHERING
279 0x90 , 0x06,//0x04, //IMG_FUNCTRL_REG
280 //De-Interlace enable
281 0x30 , 0x00,//(I1CReadByte(TW101, 0x30)|0x01)//DITLC_VSHDW_REG
282 #ifdef OUT_PIN_CONF
0xE1 , OUT_PIN_CONF, //OPIN_CFG_REG
#endif
285
286 #ifdef Enable_HelfSample
#ifdef T100A
0x79 , 0x20,
#else
0x78 , 0xa3,
#endif
#endif
293 #ifdef EnableDither
0x90 , ENCSC | ENDITHER,
0x9c , OutputBit,
#else
297 0x90 , ENCSC,
298 #endif
299 0xff , 0x00// End of register settings, bruce, 2006/01/09
300
301 };
302
C51 COMPILER V7.50 T101_UTIL 01/12/2006 13:31:12 PAGE 6
303 REGADRVAL code stInitT10xP2[]={
304 //adr , value
305 0x24 , 0xe9, //0 //0x24
306 0x25 , 0x0F, //0x25
307 //Video Register Page Setted
308 0x2E , 0x82, //HACT_START_REG
309 0x2F , 0x30, //HACT_WIDTH_REG
310 0x3F , 0x00, //SOFT_RESET_REG
311 0xc0 , 0x14, //5 //0xc0
312 0xe0 , 0x10, //0xe0
313 0x0C , 0x8a, //CHROMA_AGC_REG
314 0x18 , 0x21, //CHROMA_DTO0_REG
315 0x19 , 0xf0, //CHROMA_DTO1_REG
316 0x1A , 0x7c, //10 //CHROMA_DTO2_REG
317 0x1B , 0x0f, //CHROMA_DTO3_REG
-
318 0x30 , 0x24, //VACT_START_REG
319 0x31 , 0x61, //VACT_HEIGHT_REG
320 0x82 , 0x42, //COMB_FILTERCFG_REG
321 #ifdef T100
-
0x04 , 0xD8, //15 //HAGC_REG // Change by Sherman for Gamma Adjustment 05'12'19
0x10 , 0x27, //AGC_PKNO_REG
0x00 , 0x00, //SRCSEL_COMBF_REG
0x03 , 0x00, //COMB_FILTERMODE_REG
0x02 , 0x4B, //YC_AGC_REG
0x11 , 0xb9, //20 //AGC_PKGT_CTRL_REG
#else
329 0x04 , 0xD8, // Change by Sherman for Gamma Adjustment 05'12'19
330 0x10 , 0x27,
331 0x02 , 0x4B,
332 0x11 , 0xFF,
333 #endif
334 //Color
335 0x01 , 0x00,//(I1CReadByte(TW101+4, 0x01)|0x01), //BW_CTRL_REG
336 #ifdef T100
0x80 , 0x05,//For char clear //LUMINANCE_PKCTRL_REG
0x07 , 0x01,//For color bar clear //YC_OPCTRL_REG
0x08 , 0x70, //CONTRAST_REG // Change by Sherman for G
-amma Adjustment 05'12'19
0x0A , 0x58, //25 //SAT_REG
0x09 , 0x18, //BRIGHT_REG
#else
343 0x08 , 0x70, // Change by Sherman for Gamma Adjustment 05'12'19
344 0x09 , 0x28,
345 0x80 , 0x03,
346 #endif
347 0x2d , 0x48, // Add by Sherman 06'01'10s
348 0xff , 0x00, // End of register settings, bruce, 2006/01/09
349 };
350
351 static uCHAR cSVideo=0;
352 /****************************************************************************
353 * Public Global Variable *
354 ****************************************************************************/
355 uDWORD m_dwTemp[2];
356 uWORD m_wDWHSZ=DWHSZ;
357 uCHAR NoSignal=0;
358 #ifdef ROTATE
359 #if (defined T101A)|(defined T101)
uCHAR Dis_Mode=BOTTOM_RIGHT;
#else
C51 COMPILER V7.50 T101_UTIL 01/12/2006 13:31:12 PAGE 7
362 uCHAR Dis_Mode=TOP_LEFT;
363 #endif
364 #endif
365
366 /****************************************************************************
367 * Public Function *
368 ****************************************************************************/
369 void InitT10x(void)
370 {
371 1 uCHAR RegIndex,RegAdr;
372 1
373 1 RegIndex=0;
374 1 RegAdr=stInitT10xP0[0].ucRegAdr;
375 1 while (RegAdr != 0xFF) // bruce, 2006/01/09
376 1 {
377 2 if(RegAdr==0x30){
378 3 I2CWriteByte(TW101,RegAdr,(I2CReadByte(TW101,0x30)|0x01)); // enable Shadow
379 3 I2CWriteByte(TW101,RegAdr,(I2CReadByte(TW101,0x30)&(~0x02))| DEINTERLACE); //Bruce, 2006/01/10
380 3 }
381 2 else{
382 3 I2CWriteByte(TW101,RegAdr,stInitT10xP0[RegIndex].ucRegVal);
383 3 }
384 2 RegAdr=stInitT10xP0[++RegIndex].ucRegAdr;
385 2 }
386 1 RegIndex=0;
387 1 RegAdr=stInitT10xP2[0].ucRegAdr;
388 1 while (RegAdr != 0xFF) // bruce, 2006/01/09
389 1 {
390 2 if(RegAdr==0x01)
391 2 I2CWriteByte(TW101+4,RegAdr,(I2CReadByte(TW101+4,0x01)|0x01));// enable black level correction for 10 b
-lank-to-black pedestal
392 2 else
393 2 I2CWriteByte(TW101+4,RegAdr,stInitT10xP2[RegIndex].ucRegVal);
394 2 RegAdr=stInitT10xP2[++RegIndex].ucRegAdr;
395 2 }
396 1 //=========================================================================
397 1 // Panel specified register settings
398 1 //=========================================================================
399 1 //#if (EMPTY_ARRAY)
400 1 for(RegIndex=0;RegIndex < PanelSpecP0Cnt;RegIndex++)
401 1 {
402 2 I2CWriteByte(TW101,ucaPanelSpecAdrP0[RegIndex],ucaPanelSpecDataP0[RegIndex]);
403 2 }
404 1 //#endif
405 1
406 1 for(RegIndex=0;RegIndex < PanelSpecP2Cnt;RegIndex++)
407 1 {
408 2 I2CWriteByte(TW101+4,ucaPanelSpecAdrP2[RegIndex],ucaPanelSpecDataP2[RegIndex]);
409 2 }
410 1
411 1 #ifdef ROTATE
412 1 SET_Dismod();
413 1 #endif
414 1 }
415
416 #ifdef TCON
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