c6211dsk.h

适用于TSM320C6000系列的EDMA实验原代码

#ifndef C6211DSK_H
#define C6211DSK_H

/*******************************************************************************
* FILENAME
*   c6211dsk.h
*
* DESCRIPTION
*   DSK Header File
*
*******************************************************************************/

/* register definition for C6211dsk  */

/* define EMIF registers  */

#define EMIF_GCR 	0x1800000	/* EMIF global control      */
#define EMIF_CE0    0x1800008 	/* EMIF CE0 control         */
#define EMIF_CE1	0x1800004	/* EMIF CE1 control         */
#define EMIF_CE2	0x1800010	/* EMIF CE2 control			*/
#define EMIF_SDCTRL 0x1800018 	/* EMIF SDRAM control       */
#define EMIF_SDRP   0x180001C 	/* EMIF SDRM refresh period */
 
/* define McBSP0 registers */
#define McBSP0_DRR      0x18c0000       /* address of data receive reg.           */
#define McBSP0_DXR      0x18c0004       /* address of data transmit reg.          */
#define McBSP0_SPCR     0x18c0008       /* address of serial port contl. reg.     */
#define McBSP0_RCR      0x18c000C       /* address of receive control reg.        */
#define McBSP0_XCR      0x18c0010       /* address of transmit control reg.       */
#define McBSP0_SRGR     0x18c0014       /* address of sample rate generator       */
#define McBSP0_MCR      0x18c0018       /* address of multichannel reg.           */
#define McBSP0_RCER     0x18c001C       /* address of receive channel enable.     */
#define McBSP0_XCER     0x18c0020       /* address of transmit channel enable.    */
#define McBSP0_PCR      0x18c0024       /* address of pin control reg.            */

/* define McBSP1 registers */
#define McBSP1_DRR      0x1900000       /* address of data receive reg.           */
#define McBSP1_DXR      0x1900004       /* address of data transmit reg.          */
#define McBSP1_SPCR     0x1900008       /* address of serial port contl. reg.     */
#define McBSP1_RCR      0x190000C       /* address of receive control reg.        */
#define McBSP1_XCR      0x1900010       /* address of transmit control reg.       */
#define McBSP1_SRGR     0x1900014       /* address of sample rate generator       */
#define McBSP1_MCR      0x1900018       /* address of multichannel reg.           */
#define McBSP1_RCER     0x190001C       /* address of receive channel enable.     */
#define McBSP1_XCER     0x1900020       /* address of transmit channel enable.    */
#define McBSP1_PCR      0x1900024       /* address of pin control reg.            */

/* define L2 cache registers */
#define L2CFG           0x1840000       /* address of L2 config reg               */
#define MAR0            0x1848200       /* address of mem attribute reg           */

/* define interrupt registers                                                     */

#define IMH             0x19c0000       /* Interrupt Multiplexer High   */
#define IML             0x19c0004       /* Interrupt Multiplexer Low              */


 
/* define timer control registers                                          */

#define TIMER0_PRD          0x1940004
#define TIMER0_CTRL         0x1940000
#define TIMER0_COUNT        0x1940008
#define TIMER1_PRD          0x1980004
#define TIMER1_CTRL         0x1980000
#define TIMER1_COUNT        0x1980008

// EDMA Parameter fields
#define OPT 0x0
#define SRC 0x4
#define CNT 0x8
#define DST 0xC
#define IDX 0x10
#define LNK 0x14

// EDMA Parameter addresses 
#define EVENT0_PARAMS 0x01A00000
#define EVENT1_PARAMS EVENT0_PARAMS + 0x18
#define EVENT2_PARAMS EVENT1_PARAMS + 0x18
#define EVENT3_PARAMS EVENT2_PARAMS + 0x18
#define EVENT4_PARAMS EVENT3_PARAMS + 0x18
#define EVENT5_PARAMS EVENT4_PARAMS + 0x18
#define EVENT6_PARAMS EVENT5_PARAMS + 0x18
#define EVENT7_PARAMS EVENT6_PARAMS + 0x18
#define EVENT8_PARAMS EVENT7_PARAMS + 0x18
#define EVENT9_PARAMS EVENT8_PARAMS + 0x18
#define EVENTA_PARAMS EVENT9_PARAMS + 0x18
#define EVENTB_PARAMS EVENTA_PARAMS + 0x18
#define EVENTC_PARAMS EVENTB_PARAMS + 0x18
#define EVENTD_PARAMS EVENTC_PARAMS + 0x18
#define EVENTE_PARAMS EVENTD_PARAMS + 0x18
#define EVENTF_PARAMS EVENTE_PARAMS + 0x18
#define EVENTN_PARAMS EVENTF_PARAMS + 0x18
#define EVENTO_PARAMS EVENTN_PARAMS + 0x18

// EDMA Registers 
#define PQSR        0x01A0FFE0
#define CIPR        0x01A0FFE4
#define CIER        0x01A0FFE8
#define CCER        0x01A0FFEC
#define ER          0x01A0FFF0
#define EER         0x01A0FFF4
#define ECR         0x01A0FFF8
#define ESR         0x01A0FFFC

// QDMAs
#define QDMA_OPT 0x02000000
#define QDMA_SRC 0x02000004
#define QDMA_CNT 0x02000008
#define QDMA_DST 0x0200000C
#define QDMA_IDX 0x02000010
 
#define QDMA_S_OPT 0x02000020
#define QDMA_S_SRC 0x02000024
#define QDMA_S_CNT 0x02000028
#define QDMA_S_DST 0x0200002C
#define QDMA_S_IDX 0x02000030


/* definitions for the DSK */
#define IO_PORT 0x90080000   /* address of I/O port, only top byte has valid data */

#define INTERNAL_MEM_SIZE (0x3300)>>2
#define EXTERNAL_MEM_SIZE (0x400000)>>2
#define FLASH_SIZE 0x20000 
#define POST_SIZE 0x10000 
#define FLASH_WRITE_SIZE 0x80 
#define INTERNAL_MEM_START 0xc700
#define EXTERNAL_MEM_START 0x80000000
#define FLASH_START 0x90000000
#define POST_END    0x90010000 
#define FLASH_ADR1  0x90005555
#define FLASH_ADR2  0x90002AAA
#define FLASH_KEY1  0xAA
#define FLASH_KEY2  0x55
#define FLASH_KEY3  0xA0
#define ALL_A 0xaaaaaaaa
#define ALL_5 0x55555555
#define CE1_8  0xffffff03  /* reg to set CE1 as 8bit async */
#define CE1_32 0xffffff23  /* reg to set CE1 as 32bit async */

#endif