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📄 main.asm

📁 适用于TSM320C6000系列的EDMA实验原代码
💻 ASM
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;******************************************************************************
;* TMS320C6x ANSI C Codegen                                      Version 4.10 *
;* Date/Time created: Sun Mar 31 14:28:55 2002                                *
;******************************************************************************

;******************************************************************************
;* GLOBAL FILE PARAMETERS                                                     *
;*                                                                            *
;*   Architecture      : TMS320C620x                                          *
;*   Optimization      : Enabled at level 3                                   *
;*   Optimizing for    : Speed                                                *
;*                       Based on options: -o3, no -ms                        *
;*   Endian            : Little                                               *
;*   Interrupt Thrshld : Disabled                                             *
;*   Memory Model      : Large                                                *
;*   Calls to RTS      : Far                                                  *
;*   Pipelining        : Enabled                                              *
;*   Speculative Load  : Disabled                                             *
;*   Memory Aliases    : Presume are aliases (pessimistic)                    *
;*   Debug Info        : Debug                                                *
;*                                                                            *
;******************************************************************************

	.asg	A15, FP
	.asg	B14, DP
	.asg	B15, SP
	.global	$bss

	.file	"main.c"
	.global	_in_data
_in_data:	.usect	"mydata",8,4
	.sym	_in_data,_in_data, 51, 2, 64,, 4
	.global	_cin_data
_cin_data:	.usect	"mydata",8,4
	.sym	_cin_data,_cin_data, 51, 2, 64,, 4
	.global	_disp_buffer
_disp_buffer:	.usect	"mydata",8,4
	.sym	_disp_buffer,_disp_buffer, 51, 2, 64,, 4

	.sect	".cinit"
	.align	8
	.field  	4,32
	.field  	_flag+0,32
	.field  	57005,32			; _flag @ 0
	.sect	".text"
	.global	_flag
_flag:	.usect	.far,4,4
	.sym	_flag,_flag, 4, 2, 32
	.global	_sw_buff
_sw_buff:	.usect	.far,2,2
	.sym	_sw_buff,_sw_buff, 3, 2, 16
	.global	_hTimer
_hTimer:	.usect	.far,4,4
	.sym	_hTimer,_hTimer, 24, 2, 32, $$fake0
	.global	_hEdma
_hEdma:	.usect	.far,4,4
	.sym	_hEdma,_hEdma, 14, 2, 32
	.global	_hEdmaPing
_hEdmaPing:	.usect	.far,4,4
	.sym	_hEdmaPing,_hEdmaPing, 14, 2, 32
	.global	_hEdmaPong
_hEdmaPong:	.usect	.far,4,4
	.sym	_hEdmaPong,_hEdmaPong, 14, 2, 32
	.global	_cfgEdma
_cfgEdma:	.usect	.far,24,4
	.sym	_cfgEdma,_cfgEdma, 8, 2, 192, $$fake1

	.sect	".cinit"
	.align	8
	.field  	IR_1,32
	.field  	_cfgEdmaPing+0,32
	.field  	678559746,32			; _cfgEdmaPing._opt @ 0
	.field  	25952256,32			; _cfgEdmaPing._src @ 32
	.field  	2,32			; _cfgEdmaPing._cnt @ 64
	.field  	_in_data,32		; _cfgEdmaPing._dst @ 96
	.field  	4,32			; _cfgEdmaPing._idx @ 128
	.field  	0,32			; _cfgEdmaPing._rld @ 160
IR_1:	.set	24
	.sect	".text"
	.global	_cfgEdmaPing
_cfgEdmaPing:	.usect	.far,24,4
	.sym	_cfgEdmaPing,_cfgEdmaPing, 8, 2, 192, $$fake1

	.sect	".cinit"
	.align	8
	.field  	IR_2,32
	.field  	_cfgEdmaPong+0,32
	.field  	678559746,32			; _cfgEdmaPong._opt @ 0
	.field  	25952256,32			; _cfgEdmaPong._src @ 32
	.field  	2,32			; _cfgEdmaPong._cnt @ 64
	.field  	_cin_data,32		; _cfgEdmaPong._dst @ 96
	.field  	4,32			; _cfgEdmaPong._idx @ 128
	.field  	0,32			; _cfgEdmaPong._rld @ 160
IR_2:	.set	24
	.sect	".text"
	.global	_cfgEdmaPong
_cfgEdmaPong:	.usect	.far,24,4
	.sym	_cfgEdmaPong,_cfgEdmaPong, 8, 2, 192, $$fake1
;	c:\ti\c6000\cgtools\bin\opt6x.exe -O3 C:\TEMP\TI258_2 C:\TEMP\TI258_4 
	.sect	".text"
	.global	_start_timer1
	.sym	_start_timer1,_start_timer1, 32, 2, 0
	.func	243

;******************************************************************************
;* FUNCTION NAME: _start_timer1                                               *
;*                                                                            *
;*   Regs Modified     : A0,A3,B4,B5                                          *
;*   Regs Used         : A0,A3,B3,B4,B5                                       *
;*   Local Frame Size  : 0 Args + 0 Auto + 0 Save = 0 byte                    *
;******************************************************************************
_start_timer1:
;** --------------------------------------------------------------------------*
	.line	2
	.sym	_hTimer,0, 24, 4, 32, $$fake0
           MVKL    .S1     _hTimer,A0        ; |141| 
           MVKH    .S1     _hTimer,A0        ; |141| 
           LDW     .D1T1   *A0,A0            ; |141| 
           NOP             4
           LDW     .D1T2   *+A0(8),B4        ; |142| 
           NOP             4
           LDW     .D2T2   *B4,B5            ; |142| 
           NOP             4
           SET     .S2     B5,7,7,B5         ; |142| 
           STW     .D2T2   B5,*B4            ; |142| 
           LDW     .D1T1   *+A0(8),A0        ; |143| 
           NOP             4
           LDW     .D1T1   *A0,A3            ; |143| 
           NOP             4
           SET     .S1     A3,6,6,A3         ; |143| 
           STW     .D1T1   A3,*A0            ; |143| 
	.line	4
	.line	5
           B       .S2     B3                ; |247| 
           NOP             5
           ; BRANCH OCCURS                   ; |247| 
	.endfunc	247,000000000h,0


	.sect	".text"
	.global	_mcbsp0_write
	.sym	_mcbsp0_write,_mcbsp0_write, 32, 2, 0
	.func	212

;******************************************************************************
;* FUNCTION NAME: _mcbsp0_write                                               *
;*                                                                            *
;*   Regs Modified     : A0,A1,A3,A4,A5,B0,B4                                 *
;*   Regs Used         : A0,A1,A3,A4,A5,B0,B3,B4                              *
;*   Local Frame Size  : 0 Args + 0 Auto + 0 Save = 0 byte                    *
;******************************************************************************
_mcbsp0_write:
;** --------------------------------------------------------------------------*
	.line	2
	.sym	_out_data,4, 4, 17, 32
	.sym	_out_data,5, 4, 4, 32
	.sym	_temp,16, 4, 4, 32
	.sym	_temp,0, 4, 4, 32
           MV      .D1     A4,A5             ; |213| 
	.line	5
           MVKL    .S1     0x18c0008,A0      ; |216| 
           MVKH    .S1     0x18c0008,A0      ; |216| 
           LDW     .D1T1   *A0,A0            ; |216| 
           ZERO    .D2     B4                ; |216| 
           MVKH    .S2     0x20000,B4        ; |216| 
           NOP             2
           AND     .S2X    B4,A0,B0          ; |216| 
   [ B0]   B       .S1     L4                ; |216| 
           ZERO    .D1     A3                ; |216| 
           MVKH    .S1     0x20000,A3        ; |216| 
   [!B0]   MVKL    .S1     0x18c0008,A0      ; (P) |220| 
   [!B0]   MVKH    .S1     0x18c0008,A0      ; (P) |220| 
   [!B0]   LDW     .D1T1   *A0,A4            ; (P)  ^ |220| 
           ; BRANCH OCCURS                   ; |216| 
;** --------------------------------------------------------------------------*
           MVK     .S2     0x1,B0
           MVKL    .S1     0x18c0008,A0      ; (P) @|220| 
           NOP             2
           AND     .L1     A3,A4,A1          ; (P)  ^ |220| 
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line               : 218
;*      Loop opening brace source line : 219
;*      Loop closing brace source line : 221
;*      Known Minimum Trip Count         : 1
;*      Known Max Trip Count Factor      : 1
;*      Loop Carried Dependency Bound(^) : 7
;*      Unpartitioned Resource Bound     : 2
;*      Partitioned Resource Bound(*)    : 2
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     2*       1     
;*      .D units                     1        0     
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             1        0     
;*      Long read paths              0        0     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           1        0     (.L or .S unit)
;*      Addition ops (.LSD)          0        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             2*       1     
;*      Bound(.L .S .D .LS .LSD)     2*       1     
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 7  Schedule found with 3 iterations in parallel
;*      done
;*
;*      Loop is interruptible
;*      Collapsed epilog stages     : 2
;*      Prolog not removed
;*      Collapsed prolog stages     : 0
;*
;*      Minimum required memory pad : 0 bytes
;*
;*      Minimum safe trip count     : 1
;*----------------------------------------------------------------------------*
;*   SETUP CODE
;*
;*              MVK             0x1,B0
;*              ZERO            A4
;*
;*   SINGLE SCHEDULED ITERATION
;*
;*   C23:
;*              MVKL    .S1     0x18c0008,A0      ; |220| 
;*              MVKH    .S1     0x18c0008,A0      ; |220| 
;*      [ B0]   LDW     .D1T1   *A0,A4            ;  ^ |220| 
;*              NOP             4
;*              AND     .L1     A3,A4,A1          ;  ^ |220| 
;*      [ A1]   ZERO    .D2     B0                ;  ^ 
;*      [ B0]   B       .S2     C23               ; |220| 
;*              NOP             5
;*              ; BRANCH OCCURS                   ; |220| 
;*----------------------------------------------------------------------------*
L1:    ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L2:    ; PIPED LOOP KERNEL

   [ A1]   ZERO    .D2     B0                ;  ^ 
||         MVKH    .S1     0x18c0008,A0      ; @|220| 

   [ B0]   B       .S2     L2                ; |220| 
|| [ B0]   LDW     .D1T1   *A0,A4            ; @ ^ |220| 

           NOP             4

           AND     .L1     A3,A4,A1          ; @ ^ |220| 
||         MVKL    .S1     0x18c0008,A0      ; @@|220| 

;** --------------------------------------------------------------------------*
L3:    ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
L4:    
	.line	12
           MVKL    .S1     0x18c0004,A0      ; |223| 
           MVKH    .S1     0x18c0004,A0      ; |223| 
           STW     .D1T1   A5,*A0            ; |223| 
	.line	13
           B       .S2     B3                ; |224| 
           NOP             5
           ; BRANCH OCCURS                   ; |224| 
	.endfunc	224,000000000h,0


	.sect	".text"
	.global	_mcbsp0_read
	.sym	_mcbsp0_read,_mcbsp0_read, 36, 2, 0
	.func	227

;******************************************************************************
;* FUNCTION NAME: _mcbsp0_read                                                *
;*                                                                            *
;*   Regs Modified     : A0,A1,A3,A4,B0                                       *
;*   Regs Used         : A0,A1,A3,A4,B0,B3                                    *
;*   Local Frame Size  : 0 Args + 0 Auto + 0 Save = 0 byte                    *
;******************************************************************************
_mcbsp0_read:
;** --------------------------------------------------------------------------*
	.line	2
	.sym	_temp,1, 4, 4, 32
	.sym	_temp,0, 4, 4, 32
	.sym	_temp,4, 4, 4, 32
	.line	5
           MVKL    .S1     0x18c0008,A0      ; |231| 
           MVKH    .S1     0x18c0008,A0      ; |231| 
           LDW     .D1T1   *A0,A0            ; |231| 
           NOP             4
           AND     .S1     2,A0,A1           ; |231| 
   [ A1]   B       .S1     L8                ; |231| 
   [!A1]   MVKL    .S1     0x18c0008,A0      ; (P) |235| 
   [!A1]   MVKH    .S1     0x18c0008,A0      ; (P) |235| 
   [!A1]   LDW     .D1T1   *A0,A3            ; (P)  ^ |235| 
           NOP             2
           ; BRANCH OCCURS                   ; |231| 
;** --------------------------------------------------------------------------*
           MVK     .S2     0x1,B0
           MVKL    .S1     0x18c0008,A0      ; (P) @|235| 
           AND     .L1     2,A3,A1           ; (P)  ^ |235| 
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line               : 233
;*      Loop opening brace source line : 234
;*      Loop closing brace source line : 236
;*      Known Minimum Trip Count         : 1
;*      Known Max Trip Count Factor      : 1
;*      Loop Carried Dependency Bound(^) : 7
;*      Unpartitioned Resource Bound     : 2
;*      Partitioned Resource Bound(*)    : 2
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     2*       1     
;*      .D units                     1        0     
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             1        0     
;*      Long read paths              0        0     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           1        0     (.L or .S unit)
;*      Addition ops (.LSD)          0        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             2*       1     
;*      Bound(.L .S .D .LS .LSD)     2*       1     
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 7  Schedule found with 3 iterations in parallel
;*      done
;*
;*      Loop is interruptible
;*      Collapsed epilog stages     : 2
;*      Prolog not removed
;*      Collapsed prolog stages     : 0
;*
;*      Minimum required memory pad : 0 bytes
;*
;*      Minimum safe trip count     : 1
;*----------------------------------------------------------------------------*
;*   SETUP CODE

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