📄 direct_iir4tag.mdl
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SIGNALCOMPILER_PARAMS "depth;1;clken;off;MaskValue;1;sclr;off;"
}
Block {
BlockType Reference
Name "Delay3"
Ports [1, 1]
Position [306, 345, 344, 380]
Orientation "down"
ForegroundColor "blue"
NamePlacement "alternate"
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
sclr off
SIGNALCOMPILER_PARAMS "depth;1;clken;off;MaskValue;1;sclr;off;"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator"
Ports [0, 1]
Position [15, 13, 60, 47]
Period "1000"
PhaseDelay "10"
}
Block {
BlockType Scope
Name "Scope"
Ports [2]
Position [680, 206, 710, 239]
Location [188, 390, 512, 629]
Open off
NumInputPorts "2"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
YMin "-5~-5"
YMax "5~5"
DataFormat "StructureWithTime"
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [34, 373, 103, 420]
ForegroundColor "blue"
SourceBlock "Altelink/AltLab/SignalCompiler"
SourceType "SignalCompiler"
family "APEX 20K"
opt "Balanced"
synthtool "Others"
vstim on
SynthAct "None"
workdir "e:\\dsp_builder\\iir"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
VerilogSupport off
UniqueVHDLHierarchyName off
RegenerateIPFunctionalModel off
RunUpdatedSimulation off
JTAGCable "USB-Blaster [USB-0]"
dspb_ver "5.1"
}
Block {
BlockType Reference
Name "feedback\nAdder "
Ports [2, 1]
Position [170, 58, 205, 107]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
SourceType "Sum AlteraBlockSet"
Inputs "2"
direction "+-"
pipeline on
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;direction;+-;Inputs;2;MaskValue;1;pip"
"eline;on;"
}
Block {
BlockType Reference
Name "feedback\nAdder1"
Ports [4, 1]
Position [140, 250, 175, 300]
Orientation "left"
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
SourceType "Sum AlteraBlockSet"
Inputs "4"
direction "+"
pipeline on
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;direction;+;Inputs;4;MaskValue;1;pipe"
"line;on;"
}
Block {
BlockType Reference
Name "feedback\nAdder2"
Ports [5, 1]
Position [490, 205, 525, 255]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
SourceType "Sum AlteraBlockSet"
Inputs "5"
direction "+"
pipeline on
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;direction;+;Inputs;5;MaskValue;1;pipe"
"line;on;"
}
Block {
BlockType Reference
Name "x"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [85, 62, 150, 78]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Fractional"
nodetype "Input Port"
bwl "2"
bwr "8"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "x"
ppat "e:\\dsp_builder\\iir\\DSPBuilder_direct_iir4tag"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Signed Fractional;nodetype;Input Port;bwl;2"
";bwr;8;sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "y"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [560, 222, 625, 238]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Fractional"
nodetype "Output Port"
bwl "4"
bwr "23"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "y"
ppat "e:\\dsp_builder\\iir\\DSPBuilder_direct_iir4tag"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Signed Fractional;nodetype;Output Port;bwl;"
"4;bwr;23;sat;off;rnd;off;cst;0;LocPin;any;"
}
Line {
SrcBlock "BusConversion"
SrcPort 1
Points [10, 0; 0, -70]
DstBlock "feedback\nAdder "
DstPort 2
}
Line {
SrcBlock "feedback\nAdder "
SrcPort 1
Points [115, 0]
Branch {
DstBlock "B0"
DstPort 1
}
Branch {
DstBlock "Delay"
DstPort 1
}
}
Line {
SrcBlock "x"
SrcPort 1
DstBlock "feedback\nAdder "
DstPort 1
}
Line {
SrcBlock "Delay"
SrcPort 1
Points [0, 10]
Branch {
DstBlock "Delay1"
DstPort 1
}
Branch {
Points [0, 0]
Branch {
DstBlock "A1"
DstPort 1
}
Branch {
DstBlock "B1"
DstPort 1
}
}
}
Line {
SrcBlock "Delay1"
SrcPort 1
Points [0, 10]
Branch {
DstBlock "Delay2"
DstPort 1
}
Branch {
DstBlock "B2"
DstPort 1
}
Branch {
DstBlock "A2"
DstPort 1
}
}
Line {
SrcBlock "Delay2"
SrcPort 1
Points [0, 15]
Branch {
DstBlock "Delay3"
DstPort 1
}
Branch {
Points [0, 0]
Branch {
DstBlock "B3"
DstPort 1
}
Branch {
DstBlock "A3"
DstPort 1
}
}
}
Line {
SrcBlock "Delay3"
SrcPort 1
Points [0, 10; 0, 0]
Branch {
DstBlock "B4"
DstPort 1
}
Branch {
DstBlock "A4"
DstPort 1
}
}
Line {
SrcBlock "A2"
SrcPort 1
Points [0, 40]
DstBlock "feedback\nAdder1"
DstPort 2
}
Line {
SrcBlock "A3"
SrcPort 1
Points [-5, 0; 0, -30]
DstBlock "feedback\nAdder1"
DstPort 3
}
Line {
SrcBlock "A4"
SrcPort 1
Points [-20, 0; 0, -105]
DstBlock "feedback\nAdder1"
DstPort 4
}
Line {
SrcBlock "A1"
SrcPort 1
Points [-20, 0; 0, 110]
DstBlock "feedback\nAdder1"
DstPort 1
}
Line {
SrcBlock "feedback\nAdder1"
SrcPort 1
Points [-120, 0; 0, -110]
DstBlock "BusConversion"
DstPort 1
}
Line {
SrcBlock "B2"
SrcPort 1
DstBlock "feedback\nAdder2"
DstPort 3
}
Line {
SrcBlock "B3"
SrcPort 1
Points [10, 0; 0, -70]
DstBlock "feedback\nAdder2"
DstPort 4
}
Line {
SrcBlock "B1"
SrcPort 1
Points [10, 0; 0, 70]
DstBlock "feedback\nAdder2"
DstPort 2
}
Line {
SrcBlock "B0"
SrcPort 1
Points [20, 0; 0, 125]
DstBlock "feedback\nAdder2"
DstPort 1
}
Line {
SrcBlock "B4"
SrcPort 1
Points [15, 0; 0, -145]
DstBlock "feedback\nAdder2"
DstPort 5
}
Line {
SrcBlock "feedback\nAdder2"
SrcPort 1
DstBlock "y"
DstPort 1
}
Line {
SrcBlock "y"
SrcPort 1
DstBlock "Scope"
DstPort 2
}
Line {
SrcBlock "Pulse\nGenerator"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "x"
DstPort 1
}
Branch {
Points [460, 0; 0, 185]
DstBlock "Scope"
DstPort 1
}
}
}
}
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