📄 cascade_iir4tag.mdl
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DataFormat "StructureWithTime"
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [34, 373, 103, 420]
ForegroundColor "blue"
SourceBlock "Altelink/AltLab/SignalCompiler"
SourceType "SignalCompiler"
family "APEX 20K"
opt "Balanced"
synthtool "Others"
vstim on
SynthAct "None"
workdir "E:\\DSP_Builder\\IIR"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
VerilogSupport off
UniqueVHDLHierarchyName off
RegenerateIPFunctionalModel off
RunUpdatedSimulation off
JTAGCable "USB-Blaster [USB-0]"
dspb_ver "5.1"
}
Block {
BlockType Step
Name "Step"
Position [15, 35, 45, 65]
Time "1e-7"
SampleTime "2e-8"
}
Block {
BlockType Reference
Name "feedback\nAdder "
Ports [2, 1]
Position [315, 38, 350, 87]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
SourceType "Sum AlteraBlockSet"
Inputs "2"
direction "+-"
pipeline on
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;direction;+-;Inputs;2;MaskValue;1;pip"
"eline;on;"
}
Block {
BlockType Reference
Name "feedback\nAdder 1"
Ports [2, 1]
Position [360, 378, 395, 427]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
SourceType "Sum AlteraBlockSet"
Inputs "2"
direction "+-"
pipeline on
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;direction;+-;Inputs;2;MaskValue;1;pip"
"eline;on;"
}
Block {
BlockType Reference
Name "feedback\nAdder1"
Ports [2, 1]
Position [255, 207, 290, 258]
Orientation "left"
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
SourceType "Sum AlteraBlockSet"
Inputs "2"
direction "+"
pipeline on
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;direction;+;Inputs;2;MaskValue;1;pipe"
"line;on;"
}
Block {
BlockType Reference
Name "feedback\nAdder2"
Ports [3, 1]
Position [610, 205, 645, 255]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
SourceType "Sum AlteraBlockSet"
Inputs "3"
direction "+"
pipeline on
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;direction;+;Inputs;3;MaskValue;1;pipe"
"line;on;"
}
Block {
BlockType Reference
Name "feedback\nAdder3"
Ports [2, 1]
Position [285, 542, 320, 593]
Orientation "left"
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
SourceType "Sum AlteraBlockSet"
Inputs "2"
direction "+"
pipeline on
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;direction;+;Inputs;2;MaskValue;1;pipe"
"line;on;"
}
Block {
BlockType Reference
Name "feedback\nAdder4"
Ports [3, 1]
Position [650, 410, 685, 460]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
SourceType "Sum AlteraBlockSet"
Inputs "3"
direction "+"
pipeline on
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;direction;+;Inputs;3;MaskValue;1;pipe"
"line;on;"
}
Block {
BlockType Reference
Name "x"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [65, 42, 130, 58]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Fractional"
nodetype "Input Port"
bwl "2"
bwr "8"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "x"
ppat "E:\\DSP_Builder\\IIR\\DSPBuilder_cascade_iir4ta"
"g"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Signed Fractional;nodetype;Input Port;bwl;2"
";bwr;8;sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "y"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [705, 427, 770, 443]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Fractional"
nodetype "Output Port"
bwl "4"
bwr "23"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "y"
ppat "E:\\DSP_Builder\\IIR\\DSPBuilder_cascade_iir4ta"
"g"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Signed Fractional;nodetype;Output Port;bwl;"
"4;bwr;23;sat;off;rnd;off;cst;0;LocPin;any;"
}
Line {
SrcBlock "BusConversion"
SrcPort 1
Points [5, 0; 0, -90]
DstBlock "feedback\nAdder "
DstPort 2
}
Line {
SrcBlock "A12"
SrcPort 1
DstBlock "feedback\nAdder1"
DstPort 2
}
Line {
SrcBlock "A11"
SrcPort 1
Points [-10, 0]
DstBlock "feedback\nAdder1"
DstPort 1
}
Line {
SrcBlock "feedback\nAdder1"
SrcPort 1
Points [-75, 0; 0, -70]
DstBlock "BusConversion"
DstPort 1
}
Line {
SrcBlock "B12"
SrcPort 1
DstBlock "feedback\nAdder2"
DstPort 3
}
Line {
SrcBlock "B11"
SrcPort 1
Points [30, 0; 0, 60]
DstBlock "feedback\nAdder2"
DstPort 2
}
Line {
SrcBlock "B10"
SrcPort 1
Points [40, 0; 0, 130]
DstBlock "feedback\nAdder2"
DstPort 1
}
Line {
SrcBlock "y"
SrcPort 1
DstBlock "Scope"
DstPort 2
}
Line {
SrcBlock "Step"
SrcPort 1
DstBlock "x"
DstPort 1
}
Line {
SrcBlock "BusConv"
SrcPort 1
DstBlock "feedback\nAdder "
DstPort 1
}
Line {
SrcBlock "x"
SrcPort 1
DstBlock "G"
DstPort 1
}
Line {
SrcBlock "G"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "BusConv"
DstPort 1
}
Branch {
Points [0, -25; 515, 0; 0, 395]
DstBlock "Scope"
DstPort 1
}
}
Line {
SrcBlock "feedback\nAdder "
SrcPort 1
DstBlock "BusConv1"
DstPort 1
}
Line {
SrcBlock "BusConv1"
SrcPort 1
Points [10, 0; 0, 20]
Branch {
DstBlock "B10"
DstPort 1
}
Branch {
Points [-35, 0]
DstBlock "Delay"
DstPort 1
}
}
Line {
SrcBlock "Delay"
SrcPort 1
Points [0, 15]
Branch {
Points [0, 0]
Branch {
DstBlock "Delay1"
DstPort 1
}
Branch {
DstBlock "A11"
DstPort 1
}
}
Branch {
DstBlock "B11"
DstPort 1
}
}
Line {
SrcBlock "Delay1"
SrcPort 1
Points [0, 15]
Branch {
DstBlock "B12"
DstPort 1
}
Branch {
DstBlock "A12"
DstPort 1
}
}
Line {
SrcBlock "BusConversion1"
SrcPort 1
Points [15, 0; 0, -65]
DstBlock "feedback\nAdder 1"
DstPort 2
}
Line {
SrcBlock "A22"
SrcPort 1
DstBlock "feedback\nAdder3"
DstPort 2
}
Line {
SrcBlock "A21"
SrcPort 1
Points [-25, 0]
DstBlock "feedback\nAdder3"
DstPort 1
}
Line {
SrcBlock "feedback\nAdder3"
SrcPort 1
Points [-60, 0]
DstBlock "BusConversion1"
DstPort 1
}
Line {
SrcBlock "B22"
SrcPort 1
Points [40, 0]
DstBlock "feedback\nAdder4"
DstPort 3
}
Line {
SrcBlock "B21"
SrcPort 1
Points [30, 0; 0, -70]
DstBlock "feedback\nAdder4"
DstPort 2
}
Line {
SrcBlock "B20"
SrcPort 1
DstBlock "feedback\nAdder4"
DstPort 1
}
Line {
SrcBlock "BusConv2"
SrcPort 1
DstBlock "feedback\nAdder 1"
DstPort 1
}
Line {
SrcBlock "feedback\nAdder 1"
SrcPort 1
DstBlock "BusConv3"
DstPort 1
}
Line {
SrcBlock "BusConv3"
SrcPort 1
Points [10, 0; 0, 20]
Branch {
DstBlock "B20"
DstPort 1
}
Branch {
Points [-35, 0]
DstBlock "Delay2"
DstPort 1
}
}
Line {
SrcBlock "Delay2"
SrcPort 1
Points [0, 0; 0, 15]
Branch {
Points [0, 0]
Branch {
DstBlock "Delay3"
DstPort 1
}
Branch {
DstBlock "A21"
DstPort 1
}
}
Branch {
DstBlock "B21"
DstPort 1
}
}
Line {
SrcBlock "Delay3"
SrcPort 1
Points [0, 0; 0, 15]
Branch {
DstBlock "B22"
DstPort 1
}
Branch {
DstBlock "A22"
DstPort 1
}
}
Line {
SrcBlock "feedback\nAdder2"
SrcPort 1
Points [15, 0; 0, 110; -455, 0; 0, 50]
DstBlock "BusConv2"
DstPort 1
}
Line {
SrcBlock "feedback\nAdder4"
SrcPort 1
DstBlock "y"
DstPort 1
}
}
}
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