📄 fir4.mdl
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SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
sclr off
SIGNALCOMPILER_PARAMS "depth;1;clken;off;MaskValue;1;sclr;off;"
}
Block {
BlockType Reference
Name "Delay1"
Ports [1, 1]
Position [200, 225, 245, 275]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
sclr off
SIGNALCOMPILER_PARAMS "depth;1;clken;off;MaskValue;1;sclr;off;"
}
Block {
BlockType Reference
Name "Delay2"
Ports [1, 1]
Position [205, 320, 250, 370]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
sclr off
SIGNALCOMPILER_PARAMS "depth;1;clken;off;MaskValue;1;sclr;off;"
}
Block {
BlockType Reference
Name "Delay3"
Ports [1, 1]
Position [205, 25, 250, 75]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
sclr off
SIGNALCOMPILER_PARAMS "depth;1;clken;off;MaskValue;1;sclr;off;"
}
Block {
BlockType Reference
Name "Output"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [550, 402, 615, 418]
ForegroundColor "blue"
FontSize 10
SourceBlock "bus_alteradspbuilder/Output"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Output Port"
bwl "9"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Output"
nSgCpl "0"
SIGNALCOMPILER_PARAMS "sgn;Signed Integer;nodetype;Output Port;bwl;9;b"
"wr;0;sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "Parallel \nAdder Subtractor"
Ports [4, 1]
Position [465, 152, 500, 228]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
SourceType "Sum AlteraBlockSet"
Inputs "4"
direction "+"
pipeline on
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;direction;+;Inputs;4;MaskValue;1;pipe"
"line;on;"
}
Block {
BlockType Reference
Name "Product"
Ports [2, 1]
Position [310, 63, 375, 112]
ForegroundColor "blue"
FontSize 10
SourceBlock "arithm_alteradspbuilder/Product"
SourceType "Product AlteraBlockSet"
pipeline "2"
lpm off
eab off
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;eab;off;lpm;off;MaskValue;1;pipeline;"
"2;"
}
Block {
BlockType Reference
Name "Product1"
Ports [2, 1]
Position [315, 148, 380, 197]
ForegroundColor "blue"
FontSize 10
SourceBlock "arithm_alteradspbuilder/Product"
SourceType "Product AlteraBlockSet"
pipeline "2"
lpm off
eab off
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;eab;off;lpm;off;MaskValue;1;pipeline;"
"2;"
}
Block {
BlockType Reference
Name "Product2"
Ports [2, 1]
Position [320, 238, 385, 287]
ForegroundColor "blue"
FontSize 10
SourceBlock "arithm_alteradspbuilder/Product"
SourceType "Product AlteraBlockSet"
pipeline "0"
lpm off
eab off
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;eab;off;lpm;off;MaskValue;1;pipeline;"
"0;"
}
Block {
BlockType Reference
Name "Product3"
Ports [2, 1]
Position [330, 333, 395, 382]
ForegroundColor "blue"
FontSize 10
SourceBlock "arithm_alteradspbuilder/Product"
SourceType "Product AlteraBlockSet"
pipeline "2"
lpm off
eab off
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;eab;off;lpm;off;MaskValue;1;pipeline;"
"2;"
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [634, 23, 703, 70]
ForegroundColor "blue"
SourceBlock "Altelink/AltLab/SignalCompiler"
SourceType "SignalCompiler"
family "APEX 20K"
opt "Balanced"
synthtool "Others"
vstim on
SynthAct "None"
workdir "e:\\dsp_builder\\fir"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
VerilogSupport off
UniqueVHDLHierarchyName off
RegenerateIPFunctionalModel off
RunUpdatedSimulation off
JTAGCable "USB-Blaster [USB-0]"
dspb_ver "5.1"
}
Block {
BlockType Reference
Name "vout"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [540, 182, 605, 198]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Output"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Output Port"
bwl "20"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Output"
nSgCpl "0"
SIGNALCOMPILER_PARAMS "sgn;Signed Integer;nodetype;Output Port;bwl;20;"
"bwr;0;sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "xin"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [85, 42, 150, 58]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "9"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "xin"
ppat "e:\\dsp_builder\\fir\\DSPBuilder_fir4"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Signed Integer;nodetype;Input Port;bwl;9;bw"
"r;0;sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "xin1"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [90, 92, 155, 108]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "9"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "xin1"
ppat "e:\\dsp_builder\\fir\\DSPBuilder_fir4"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Signed Integer;nodetype;Input Port;bwl;9;bw"
"r;0;sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "xin2"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [90, 187, 155, 203]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "9"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "xin2"
ppat "e:\\dsp_builder\\fir\\DSPBuilder_fir4"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Signed Integer;nodetype;Input Port;bwl;9;bw"
"r;0;sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "xin3"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [95, 287, 160, 303]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "9"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "xin3"
ppat "e:\\dsp_builder\\fir\\DSPBuilder_fir4"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Signed Integer;nodetype;Input Port;bwl;9;bw"
"r;0;sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "xin4"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [100, 387, 165, 403]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "9"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "xin4"
ppat "e:\\dsp_builder\\fir\\DSPBuilder_fir4"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Signed Integer;nodetype;Input Port;bwl;9;bw"
"r;0;sat;off;rnd;off;cst;0;LocPin;any;"
}
Line {
SrcBlock "Delay"
SrcPort 1
Points [25, 0; 0, 5]
Branch {
Points [0, 50; -95, 0]
DstBlock "Delay1"
DstPort 1
}
Branch {
DstBlock "Product1"
DstPort 1
}
}
Line {
SrcBlock "Delay1"
SrcPort 1
Points [0, 0; 30, 0]
Branch {
Points [0, 60; -90, 0]
DstBlock "Delay2"
DstPort 1
}
Branch {
DstBlock "Product2"
DstPort 1
}
}
Line {
SrcBlock "Delay2"
SrcPort 1
Points [35, 0]
Branch {
DstBlock "Product3"
DstPort 1
}
Branch {
Points [0, 65]
DstBlock "Output"
DstPort 1
}
}
Line {
SrcBlock "Product"
SrcPort 1
Points [60, 0; 0, 70]
DstBlock "Parallel \nAdder Subtractor"
DstPort 1
}
Line {
SrcBlock "Product1"
SrcPort 1
Points [0, 5]
DstBlock "Parallel \nAdder Subtractor"
DstPort 2
}
Line {
SrcBlock "Product2"
SrcPort 1
Points [25, 0; 0, -65]
DstBlock "Parallel \nAdder Subtractor"
DstPort 3
}
Line {
SrcBlock "Product3"
SrcPort 1
Points [30, 0; 0, -140]
DstBlock "Parallel \nAdder Subtractor"
DstPort 4
}
Line {
SrcBlock "Parallel \nAdder Subtractor"
SrcPort 1
DstBlock "vout"
DstPort 1
}
Line {
SrcBlock "xin"
SrcPort 1
DstBlock "Delay3"
DstPort 1
}
Line {
SrcBlock "Delay3"
SrcPort 1
Points [10, 0; 0, 25]
Branch {
Points [0, 45; -85, 0; 0, 35]
DstBlock "Delay"
DstPort 1
}
Branch {
DstBlock "Product"
DstPort 1
}
}
Line {
SrcBlock "xin1"
SrcPort 1
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "xin2"
SrcPort 1
Points [140, 0]
DstBlock "Product1"
DstPort 2
}
Line {
SrcBlock "xin3"
SrcPort 1
Points [140, 0]
DstBlock "Product2"
DstPort 2
}
Line {
SrcBlock "xin4"
SrcPort 1
Points [145, 0]
DstBlock "Product3"
DstPort 2
}
}
}
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