fir16tapaltblk.xml

在matlab下用DSPbuilder实现的16阶FIR滤波器

            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>-22</pvalue>
         </parameters_db>
         <port_db>
         </port_db>
         <nparameter>8</nparameter>
      </db_block>
      <db_block>
         <instancename>h5</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>12</instancenumber>
         <inport>0</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>Constant</pvalue>
            <pname>bwl</pname>
            <pvalue>9</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>-12</pvalue>
         </parameters_db>
         <port_db>
         </port_db>
         <nparameter>8</nparameter>
      </db_block>
      <db_block>
         <instancename>h6</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>13</instancenumber>
         <inport>0</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>Constant</pvalue>
            <pname>bwl</pname>
            <pvalue>9</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>46</pvalue>
         </parameters_db>
         <port_db>
         </port_db>
         <nparameter>8</nparameter>
      </db_block>
      <db_block>
         <instancename>h7</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>14</instancenumber>
         <inport>0</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>Constant</pvalue>
            <pname>bwl</pname>
            <pvalue>9</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>106</pvalue>
         </parameters_db>
         <port_db>
         </port_db>
         <nparameter>8</nparameter>
      </db_block>
      <db_block>
         <instancename>h8</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>15</instancenumber>
         <inport>0</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>Constant</pvalue>
            <pname>bwl</pname>
            <pvalue>9</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>106</pvalue>
         </parameters_db>
         <port_db>
         </port_db>
         <nparameter>8</nparameter>
      </db_block>
      <db_block>
         <instancename>h9</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>16</instancenumber>
         <inport>0</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>Constant</pvalue>
            <pname>bwl</pname>
            <pvalue>9</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>46</pvalue>
         </parameters_db>
         <port_db>
         </port_db>
         <nparameter>8</nparameter>
      </db_block>
      <db_block>
         <instancename>vout</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>17</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>OutputPort</pvalue>
            <pname>bwl</pname>
            <pvalue>20</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>ParallelAdderSubtractor</srcblk>
            <srcport>1</srcport>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>x16</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>18</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>OutputPort</pvalue>
            <pname>bwl</pname>
            <pvalue>9</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>xin</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>19</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>InputPort</pvalue>
            <pname>bwl</pname>
            <pvalue>9</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>ParallelAdderSubtractor</instancename>
         <sourcename>SumAlteraBlockSet</sourcename>
         <instancenumber>20</instancenumber>
         <inport>4</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>clken</pname>
            <pvalue>off</pvalue>
            <pname>direction</pname>
            <pvalue>+</pvalue>
            <pname>Inputs</pname>
            <pvalue>4</pvalue>
            <pname>MaskValue</pname>
            <pvalue>1</pvalue>
            <pname>pipeline</pname>
            <pvalue>on</pvalue>
         </parameters_db>
         <port_db>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>vout</dstblk>
         </port_db>
         <nparameter>6</nparameter>
      </db_block>
   </block_dspbuilder>
<top_sources>
	<library></library>
</top_sources>
   <top_parameters>
      <starttime>0.0</starttime>
      <stoptime>10</stoptime>
      <fixedstep>auto</fixedstep>
      <nsubsystem>0</nsubsystem>
      <nblocks>20</nblocks>
   </top_parameters>
   <top_signalcompiler>
      <family>APEX 20K</family>
      <opt>Balanced</opt>
      <synthtool>Others</synthtool>
      <vstim>on</vstim>
      <SynthAct>None</SynthAct>
      <workdir>E:\DSP_Builder\fir</workdir>
      <Procetype>prod</Procetype>
      <UseReset>on</UseReset>
      <ResetPin>Active High</ResetPin>
      <ClockPin>Output to Pin</ClockPin>
      <ClockPeriod>20</ClockPeriod>
      <UseSignalTap>off</UseSignalTap>
      <CreatePtfFile>off</CreatePtfFile>
      <SignalTapDepth>128</SignalTapDepth>
      <VerilogSupport>off</VerilogSupport>
      <JTAGCable>USB-Blaster [USB-0]</JTAGCable>
      <bContainMegaCoreIpTb>0</bContainMegaCoreIpTb>
   </top_signalcompiler>
</FIR16tap>