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📄 fir.mdl

📁 在matlab下用DSPbuilder实现的16阶FIR滤波器
💻 MDL
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      LockScale		      off
      RndMeth		      "Zero"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Scope
      Floating		      off
      ModelBased	      off
      TickLabels	      "OneTimeTick"
      ZoomMode		      "on"
      Grid		      "on"
      TimeRange		      "auto"
      YMin		      "-5"
      YMax		      "5"
      SaveToWorkspace	      off
      SaveName		      "ScopeData"
      LimitDataPoints	      on
      MaxDataPoints	      "5000"
      Decimation	      "1"
      SampleInput	      off
      SampleTime	      "0"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      PortCounts	      "[]"
      SFunctionModules	      "''"
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      Sum
      IconShape		      "rectangular"
      Inputs		      "++"
      InputSameDT	      on
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Trigonometry
      Operator		      "sin"
      OutputSignalType	      "auto"
      SampleTime	      "-1"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "fir"
    Location		    [168, 188, 851, 558]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Reference
      Name		      "Chirp Signal"
      Ports		      [0, 1]
      Position		      [15, 30, 45, 60]
      SourceBlock	      "simulink/Sources/Chirp Signal"
      SourceType	      "chirp"
      ShowPortLabels	      on
      f1		      "0.1"
      T			      "10"
      f2		      "1"
      VectorParams1D	      on
    }
    Block {
      BlockType		      Reference
      Name		      "Delay"
      Ports		      [1, 1]
      Position		      [200, 130, 245, 180]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "store_alteradspbuilder/Delay"
      SourceType	      "Delay AlteraBlockSet"
      depth		      "1"
      clken		      off
      MaskValue		      "1"
      sclr		      off
      SIGNALCOMPILER_PARAMS   "depth;1;clken;off;MaskValue;1;sclr;off;"
    }
    Block {
      BlockType		      Reference
      Name		      "Delay1"
      Ports		      [1, 1]
      Position		      [200, 225, 245, 275]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "store_alteradspbuilder/Delay"
      SourceType	      "Delay AlteraBlockSet"
      depth		      "1"
      clken		      off
      MaskValue		      "1"
      sclr		      off
      SIGNALCOMPILER_PARAMS   "depth;1;clken;off;MaskValue;1;sclr;off;"
    }
    Block {
      BlockType		      Reference
      Name		      "Delay2"
      Ports		      [1, 1]
      Position		      [205, 320, 250, 370]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "store_alteradspbuilder/Delay"
      SourceType	      "Delay AlteraBlockSet"
      depth		      "1"
      clken		      off
      MaskValue		      "1"
      sclr		      off
      SIGNALCOMPILER_PARAMS   "depth;1;clken;off;MaskValue;1;sclr;off;"
    }
    Block {
      BlockType		      Reference
      Name		      "Gain"
      Ports		      [1, 1]
      Position		      [320, 82, 380, 128]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "arithm_alteradspbuilder/Gain"
      SourceType	      "Gain AlteraBlockSet"
      vgain		      "63"
      BusType		      "Signed Integer"
      bwl		      "8"
      bwr		      "0"
      pipeline		      "0"
      lpm		      off
      clken		      off
      MaskValue		      "1"
      gain		      "63"
      SIGNALCOMPILER_PARAMS   "BusType;Signed Integer;bwl;8;bwr;0;pipeline;0;g"
"ain;63;clken;off;MaskValue;1;lpm;off;"
    }
    Block {
      BlockType		      Reference
      Name		      "Gain1"
      Ports		      [1, 1]
      Position		      [320, 132, 380, 178]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "arithm_alteradspbuilder/Gain"
      SourceType	      "Gain AlteraBlockSet"
      vgain		      "127"
      BusType		      "Signed Integer"
      bwl		      "8"
      bwr		      "0"
      pipeline		      "0"
      lpm		      off
      clken		      off
      MaskValue		      "1"
      gain		      "127"
      SIGNALCOMPILER_PARAMS   "BusType;Signed Integer;bwl;8;bwr;0;pipeline;0;g"
"ain;127;clken;off;MaskValue;1;lpm;off;"
    }
    Block {
      BlockType		      Reference
      Name		      "Gain2"
      Ports		      [1, 1]
      Position		      [325, 227, 385, 273]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "arithm_alteradspbuilder/Gain"
      SourceType	      "Gain AlteraBlockSet"
      vgain		      "127"
      BusType		      "Signed Integer"
      bwl		      "8"
      bwr		      "0"
      pipeline		      "0"
      lpm		      off
      clken		      off
      MaskValue		      "1"
      gain		      "127"
      SIGNALCOMPILER_PARAMS   "BusType;Signed Integer;bwl;8;bwr;0;pipeline;0;g"
"ain;127;clken;off;MaskValue;1;lpm;off;"
    }
    Block {
      BlockType		      Reference
      Name		      "Gain3"
      Ports		      [1, 1]
      Position		      [335, 322, 395, 368]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "arithm_alteradspbuilder/Gain"
      SourceType	      "Gain AlteraBlockSet"
      vgain		      "63"
      BusType		      "Signed Integer"
      bwl		      "8"
      bwr		      "0"
      pipeline		      "0"
      lpm		      off
      clken		      off
      MaskValue		      "1"
      gain		      "63"
      SIGNALCOMPILER_PARAMS   "BusType;Signed Integer;bwl;8;bwr;0;pipeline;0;g"
"ain;63;clken;off;MaskValue;1;lpm;off;"
    }
    Block {
      BlockType		      Gain
      Name		      "Gain4"
      Position		      [85, 30, 115, 60]
      Gain		      "127"
      ParameterDataTypeMode   "Inherit via internal rule"
      OutDataTypeMode	      "Inherit via internal rule"
      SaturateOnIntegerOverflow	off
    }
    Block {
      BlockType		      Reference
      Name		      "Parallel \nAdder Subtractor"
      Ports		      [4, 1]
      Position		      [465, 152, 500, 228]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
      SourceType	      "Sum AlteraBlockSet"
      Inputs		      "4"
      direction		      "+"
      pipeline		      on
      clken		      off
      MaskValue		      "1"
      SIGNALCOMPILER_PARAMS   "clken;off;direction;+;Inputs;4;MaskValue;1;pipe"
"line;on;"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope"
      Ports		      [2]
      Position		      [655, 160, 685, 240]
      Location		      [425, 172, 749, 411]
      Open		      off
      NumInputPorts	      "2"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
      }
      YMin		      "-5~-5"
      YMax		      "5~5"
      DataFormat	      "StructureWithTime"
    }
    Block {
      BlockType		      Reference
      Name		      "SignalCompiler"
      Ports		      []
      Position		      [29, 248, 98, 295]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "Altelink/AltLab/SignalCompiler"
      SourceType	      "SignalCompiler"
      family		      "APEX 20K"
      opt		      "Balanced"
      synthtool		      "Others"
      vstim		      on
      SynthAct		      "None"
      workdir		      "E:\\DSP_Builder\\fir"
      Procetype		      "prod"
      UseReset		      on
      ResetPin		      "Active High"
      ClockPin		      "Output to Pin"
      ClockPeriod	      "20"
      UseSignalTap	      off
      CreatePtfFile	      off
      SignalTapDepth	      "128"
      VerilogSupport	      off
      UniqueVHDLHierarchyName off
      RegenerateIPFunctionalModel off
      RunUpdatedSimulation    off
      JTAGCable		      "USB-Blaster [USB-0]"
      dspb_ver		      "5.1"
    }
    Block {
      BlockType		      Reference
      Name		      "vout"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [540, 182, 605, 198]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "18"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
      SIGNALCOMPILER_PARAMS   "sgn;Signed Integer;nodetype;Output Port;bwl;18;"
"bwr;0;sat;off;rnd;off;cst;0;LocPin;any;"
    }
    Block {
      BlockType		      Reference
      Name		      "xin"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [90, 97, 155, 113]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "bus_alteradspbuilder/Input"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Input Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "xin"
      ppat		      "E:\\DSP_Builder\\fir\\DSPBuilder_fir"
      nSgCpl		      "1"
      SIGNALCOMPILER_PARAMS   "sgn;Signed Integer;nodetype;Input Port;bwl;8;bw"
"r;0;sat;off;rnd;off;cst;0;LocPin;any;"
    }
    Line {
      SrcBlock		      "Delay"
      SrcPort		      1
      Points		      [0, 0; 30, 0]
      Branch {
	DstBlock		"Gain1"
	DstPort			1
      }
      Branch {
	Points			[0, 55; -95, 0]
	DstBlock		"Delay1"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "xin"
      SrcPort		      1
      Points		      [0, 0; 15, 0]
      Branch {
	DstBlock		"Gain"
	DstPort			1
      }
      Branch {
	Points			[0, 50]
	DstBlock		"Delay"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Delay1"
      SrcPort		      1
      Points		      [0, 0; 30, 0]
      Branch {
	Points			[0, 0]
	DstBlock		"Gain2"
	DstPort			1
      }
      Branch {
	Points			[0, 60; -90, 0]
	DstBlock		"Delay2"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Delay2"
      SrcPort		      1
      DstBlock		      "Gain3"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Gain"
      SrcPort		      1
      Points		      [55, 0; 0, 55]
      DstBlock		      "Parallel \nAdder Subtractor"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Gain1"
      SrcPort		      1
      Points		      [35, 0; 0, 25]
      DstBlock		      "Parallel \nAdder Subtractor"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Gain2"
      SrcPort		      1
      Points		      [25, 0; 0, -50]
      DstBlock		      "Parallel \nAdder Subtractor"
      DstPort		      3
    }
    Line {
      SrcBlock		      "Gain3"
      SrcPort		      1
      Points		      [30, 0; 0, -125]
      DstBlock		      "Parallel \nAdder Subtractor"
      DstPort		      4
    }
    Line {
      SrcBlock		      "Parallel \nAdder Subtractor"
      SrcPort		      1
      DstBlock		      "vout"
      DstPort		      1
    }
    Line {
      SrcBlock		      "vout"
      SrcPort		      1
      Points		      [30, 0]
      DstBlock		      "Scope"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Chirp Signal"
      SrcPort		      1
      DstBlock		      "Gain4"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Gain4"
      SrcPort		      1
      Points		      [10, 0]
      Branch {
	Points			[0, 40; -65, 0; 0, 20]
	DstBlock		"xin"
	DstPort			1
      }
      Branch {
	Points			[475, 0; 0, 135]
	DstBlock		"Scope"
	DstPort			1
      }
    }
  }
}

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